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Single Cycle
Datapath
° Combinational Elements
° Storage Elements
• Clocking methodology
Combinational Logic Elements (Basic Building
Blocks) CarryIn
° Adder A
32
Adder
Sum
32
B Carry
32
Select
° MUX
A
32
MUX
Y
32
B
32
OP
° ALU A
32
ALU
Result
32
B
32
Verilog Implementation of Basic
Blocks
assign y = (select) ? a: b;
endmodule
Storage Element: Register (Basic Building
Block)
° Register Write Enable
• Similar to the D Flip Flop except
Data In Data Out
- 32-bit input and output
32 32
- Write Enable input
• Write Enable:
Clk
- negated (0): Data Out will not
change
- asserted (1): Data Out will
become Data In
Verilog Implementation of Basic
Blocks
Clk
. . . .
. . . .
. . . .
° Instruction Fetch
Clk PC
Next Address
Logic
Address
Instruction Word
Instruction
Memory 32
3b: Add &
Subtract
° R[rd] <- R[rs] op R[rt] Example: addu rd, rs, rt
• Ra, Rb, and Rw come from instruction’s rs, rt, and rd fields
• ALUctr and RegWr: control logic after decoding the
instruction
31 26 21 16 11 6 0
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
Rd Rs Rt
RegWr ALUctr
5 5 5
busA
Rw Ra Rb
busW 32 Result
ALU
32 32-bit
32 32
Registers
Clk busB
32
Register-Register Timing: One complete
Clk
cycle
Clk-to-Q
PC Old Value New Value
Instruction Memory Access Time
Rs, Rt, Rd, Old Value New Value
Op, Func
Delay through Control Logic
ALUctr Old Value New Value
Rd Rs Rt
RegWr 5 5 ALUctr Register Write
5
Occurs Here
busA
Rw Ra Rb
busW 32 Result
ALU
32 32-bit
32 Registers 32
Clk busB
32
3c: Logical Operations with
°
Immediate
R[rt] <- R[rs] op ZeroExt[imm16] ]
31 26 21 16 11 0
op rs rt immediate
6 bits 5 bits 5 bits rd? 16 bits
31 16 15 0
0000000000000000 immediate
16 bits 16 bits
Rd Rt
RegDst
Mux
Rs Rt? ALUctr
RegWr 5 5 5
busA
Rw Ra Rb
busW 32 Result
32 32-bit
ALU
32 Registers 32
Clk busB
32
Mux
ZeroExt
imm16
16 32
ALUSrc
3d: Load
°
Operations
R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16
31 26 21 16 11 0
op rs rt immediate
6 bits 5 bits 5 bits rd 16 bits
Rd Rt
RegDst
Mux
Rs Rt?
RegWr 5 ALUctr
5 5
busA W_Src
Rw Ra Rb
busW 32
32 32-bit
ALU
32 Registers 32
Clk busB MemWr
Mux
32
Mux
WrEn Adr
Extender
Data In 32
32 ?? Data
imm16 32
16 Memory
Clk
ALUSrc
ExtOp
3e: Store
Operations
° Mem[ R[rs] + SignExt[imm16] <- R[rt] ] Example: sw rt, rs, imm16
31 26 21 16 0
op rs rt immediate
6 bits 5 bits 5 bits 16 bits
Rd Rt ALUctr MemWr W_Src
RegDst
Mux
Rs Rt
RegWr 5 5 5
busA
Rw Ra Rb
busW 32
32 32-bit
ALU
32 Registers 32
Clk busB
x
Mu
Mux
32
WrEn Adr
Extender
Data In 32 32
imm16 Data
32
16 Memory
Clk
ExtOp ALUSrc
3f: The Branch
Instruction
31 26 21 16 0
op rs rt immediate
6 bits 5 bits 5 bits 16 bits
31 26 21 16 0
op rs rt immediate
6 bits 5 bits 5 bits 16 bits
Inst Address Cond
nPC_sel Rs Rt
4 RegWr 5 5 5
Adder
32 busA
Rw Ra Rb
00
busW
Equal?
32 32-bit 32
Mux
Registers
PC
Clk busB
32
Adder
PC Ext
imm16
Clk
Putting it All Together: A Single Cycle
Datapath
Instruction<31:0>
<21:25>
<16:20>
<11:15>
Inst
<0:15>
Memory
Adr
Rs Rt Rd Imm16
busA
busW Rw Ra Rb =
00
32 32-bit 32
ALU
Mux
32 Registers busB 32 0
PC
Mux
32
Mux
Adder
1 Data In
PC Ext
16 Memory
Clk
ExtOp ALUSrc
An Abstract View of the Critical
° Path file and ideal memory:
Register
• The CLK input is a factor ONLY during write operation
• During read operation, behave as combinational logic:
- Address valid => Output valid after “access time.”
Critical Path (Load Operation) =
PC’s Clk-to-Q +
Ideal Instruction Memory’s Access Time +
Instruction Register File’s Access Time +
Instruction ALU to Perform a 32-bit Add +
Memory
Rd Rs Rt Imm Data Memory Access Time +
5 5 5 16 Setup Time for Register File Write +
Instruction Clock Skew
Address
A Data
Rw Ra Rb 32
Next Address
32 Address
32 Ideal
32 32-bit
ALU
Data
PC
Registers Data In
B Memory
Clk
Clk
Clk
32
An Abstract View of the
Implementation
Ideal Control
Instruction Control Signals Conditions
Instruction
Memory
Rd Rs Rt
5 5 5
Instruction
Address
A Data
Rw Ra Rb 32 Data
Next Address
32 Address
32 Ideal Out
32 32-bit
ALU
Data
PC
Clk Clk
32
Clk
Datapath
Recap: A Single Cycle Datapath
° Rs, Rt, Rd and Imed16 hardwired into datapath from Fetch Unit
° We have everything except control signals (underline)
• Today’s lecture will show you how to generate the control signals
Instruction<31:0>
nPC_sel Instruction
<21:25>
<16:20>
<11:15>
<0:15>
Rd Rt Fetch Unit
Clk
RegDst 1 Mux 0
Rs Rt Rt Rs Rd Imm16
RegWr 5 5 5 ALUctr Zero
busA MemWr MemtoReg
Rw Ra Rb
busW 32
32 32-bit
ALU
32 0
Registers busB 0 32
Clk
Mux
32
Mux
32
WrEn Adr 1
Extender
1 Data In 32
imm16 Data
32
16 Memory
Clk
ALUSrc
ExtOp
Recap: Meaning of the Control
Signals
° nPC_MUX_sel: 0 PC <– PC + 4
1 PC <– PC + 4 + SignExt(Im16) || 00
nPC_MUX_sel
Inst
Memory
Adr
4
Adder
00
Mux
PC
Adder
imm16
PC Ext
Clk
Recap: Meaning of the Control
°
Signals“zero”, “sign”
ExtOp: ° MemWr: 1 write memory
° MemtoReg: 0 ALU; 1 Mem
° ALUsrc: 0 regB; 1 immed
° RegDst: 0 “rt”; 1 “rd”
° ALUctr: “add”, “sub”, “or”
° RegWr: 1 write register
RegDst
Equal ALUctr MemWr MemtoReg
Rd Rt
1 0
Rs Rt
RegWr 5 5 5
busA
Rw Ra Rb =
busW
32 32-bit 32
ALU
32 Registers busB 0
0 32
Mux
32
Mux
1 Data In
Data 1
imm16 32
16 Memory
Clk
ExtOp ALUSrc
RTL: The Add
Instruction
31 26 21 16 11 6 0
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
Inst
Memory Instruction<31:0>
Adr
nPC_MUX_sel
4
Adder
00
Mux
PC
Adder
Clk
imm16
PC Ext
The Single Cycle Datapath during
Add 31 26 21 16 11 6 0
op rs rt rd shamt funct
<21:25>
<16:20>
<11:15>
<0:15>
Rd Rt Fetch Unit
RegDst = 1 Clk
1 Mux 0
Rs Rt ALUctr = Add Rt Rs Rd Imm16
RegWr = 1 5 5 5 MemtoReg = 0
busA Zero MemWr = 0
Rw Ra Rb
busW 32
32 32-bit
ALU
32 0
Registers busB 0 32
Clk
Mux
32
Mux
32
WrEn Adr 1
Extender
1 Data In 32
imm16 Data
32
16 Memory
Clk
ALUSrc = 0
ExtOp = x
Instruction Fetch Unit at the End of
Add
° PC <- PC + 4
• This is the same for all instructions except: Branch and Jump
Inst
Memory Instruction<31:0>
Adr
nPC_MUX_sel
4
Adder
0
00
Mux
PC
1
Adder
Clk
imm16
The Single Cycle Datapath during Or
Immediate
31 26 21 16 0
op rs rt immediate
<21:25>
<16:20>
<11:15>
<0:15>
Rd Rt Fetch Unit
RegDst = Clk
1 Mux 0
Rs Rt ALUctr = Rt Rs Rd Imm16
RegWr = 5 5 5 MemtoReg =
busA Zero MemWr =
Rw Ra Rb
busW 32
32 32-bit
ALU
32 0
Registers busB 0 32
Clk
Mux
32
Mux
32
WrEn Adr 1
Extender
1 Data In 32
imm16 Data
32
16 Memory
Clk
ALUSrc =
ExtOp =
The Single Cycle Datapath during
Load 31 26 21 16 0
op rs rt immediate
<21:25>
<16:20>
<11:15>
<0:15>
Rd Rt Fetch Unit
RegDst = 0 Clk
1 Mux 0
Rs Rt ALUctr Rt Rs Rd Imm16
RegWr = 1 5 5 5 = Add MemtoReg = 1
busA Zero MemWr = 0
Rw Ra Rb
busW 32
32 32-bit
ALU
32 0
Registers busB 0 32
Clk
Mux
32
Mux
WrEn Adr 1
Extender
1 Data In 32
imm16 Data 32
32
16 Memory
Clk
ALUSrc = 1
ExtOp = 1
The Single Cycle Datapath during
Store 31 26 21 16 0
op rs rt immediate
<21:25>
<16:20>
<11:15>
<0:15>
Rd Rt Fetch Unit
RegDst = Clk
1 Mux 0
Rs Rt ALUctr = Rt Rs Rd Imm16
RegWr = 5 5 5
MemtoReg =
busA Zero MemWr =
Rw Ra Rb
busW 32
32 32-bit
ALU
32 0
Registers busB 0 32
Clk
Mux
32
Mux
32
WrEn Adr 1
Extender
1 Data In 32
imm16 Data
32
16 Memory
Clk
ALUSrc =
ExtOp =
The Single Cycle Datapath during
Store 31 26 21 16 0
op rs rt immediate
<21:25>
<16:20>
<11:15>
<0:15>
Rd Rt Fetch Unit
RegDst = x Clk
1 Mux 0
Rs Rt ALUctr Rt Rs Rd Imm16
RegWr = 0 5 5 5 = Add
MemtoReg = x
busA Zero MemWr = 1
Rw Ra Rb
busW 32
32 32-bit
ALU
32 0
Registers busB 0 32
Clk
Mux
32
Mux
32
WrEn Adr 1
Extender
1 Data In 32
imm16 Data
32
16 Memory
Clk
ALUSrc = 1
ExtOp = 1
The Single Cycle Datapath during
Branch31 26 21 16 0
op rs rt immediate
<21:25>
<16:20>
<11:15>
<0:15>
Rd Rt Fetch Unit
RegDst = x Clk
1 Mux 0
RegWr = 0 Rs Rt ALUctr =Sub Rt Rs Rd Imm16
5 5 5 MemtoReg = x
busA Zero MemWr = 0
Rw Ra Rb
busW 32
32 32-bit
ALU
32 0
Registers busB 0 32
Clk
Mux
32
Mux
32
WrEn Adr 1
Extender
1 Data In 32
imm16 Data
32
16 Memory
Clk
ALUSrc = 0
ExtOp = x
Instruction Fetch Unit at the End of
Branch31 26 21 16 0
op rs rt immediate
Inst
Memory Instruction<31:0>
nPC_sel Adr
Zero
° What is encoding of nPC_sel?
• Direct MUX select?
nPC_MUX_sel
• Branch / not branch
4
° Let’s choose second option
Adder
0 x 0
Mux
1 0 0
PC
1 1 1
1
Adder
Clk
imm16
Step 4: Given Datapath: RTL ->
Control
Instruction<31:0>
<21:25>
Inst
<21:25>
<16:20>
<11:15>
<0:15>
Memory
Adr
Op Fun Rt Rs Rd Imm16
Control
DATA PATH
A Summary of Control
Signals
31 26 21 16 11 6 0
R-type op rs rt rd shamt funct add, sub
func
ALU ALUctr
op Main 6
ALUop Control 3
6 Control
(Local)
N
ALU
The Encoding of
ALUop
func
op 6 ALU ALUctr
Main
ALUop Control
6 Control 3
(Local)
N
31 26 21 16 11 6 0
R-type op rs rt rd shamt funct
P. 286 text:
funct<5:0> Instruction Operation ALUctr ALUctr<2:0> ALU Operation
10 0000 add 000 And
10 0010 subtract ALU
001 Or
10 0100 and 010 Add
10 0101 or 110 Subtract
10 1010 set-on-less-than 111 Set-on-less-than
The Truth Table for
ALUctr
funct<3:0> Instruction Op.
0000 add
ALUop R-type ori lw sw beq 0010 subtract
(Symbolic) “R-type” Or Add Add Subtract 0100 and
ALUop<2:0> 1 00 0 10 0 00 0 00 0 01 0101 or
1010 set-on-less-than
° RegWr: <=_____________
ALUSrc
RegDst
MemtoReg
MemWrite
Branch
Jump
ExtOp
ALUop<2>
ALUop<1>
ALUop<0>
Putting it All Together: A Single Cycle
Processor ALUop
ALU ALUctr
RegDst 3 func Control
op Main 3
ALUSrc Instr<5:0> 6
6 Control
Instr<31:26> : Instruction<31:0>
nPC_sel
Instruction
<21:25>
<16:20>
<11:15>
<0:15>
Rd Rt Fetch Unit
RegDst Clk
1 Mux 0
Rs Rt Rt Rs Rd Imm16
RegWr 5 5 5 ALUctr
busA Zero MemWr MemtoReg
Rw Ra Rb
busW 32
32 32-bit
ALU
32 0
Registers busB 0 32
Clk
Mux
32
Mux
32
WrEn Adr 1
Extender
1 Data In 32
imm16 Data
32
Instr<15:0> 16 Memory
Clk
ALUSrc
ExtOp
Recap: An Abstract View of the Critical Path
° (Load)
Register file and ideal memory:
• The CLK input is a factor ONLY during write operation
• During read operation, behave as combinational logic:
- Address valid => Output valid after “access time.”
Critical Path (Load Operation) =
PC’s Clk-to-Q +
Ideal Instruction Memory’s Access Time +
Instruction Register File’s Access Time +
Instruction ALU to Perform a 32-bit Add +
Memory
Rd Rs Rt Imm Data Memory Access Time +
5 5 5 16 Setup Time for Register File Write +
Instruction Clock Skew
Address
A Data
Rw Ra Rb 32
Next Address
32 Address
32 Ideal
32 32-bit
ALU
Data
PC
Registers Data In
B Memory
Clk Clk
32
Clk
Worst Case Timing
Clk
(Load)
Clk-to-Q
PC Old Value New Value
Instruction Memory Access Time
Rs, Rt, Rd, Old Value New Value
Op, Func
Delay through Control Logic
ALUctr Old Value New Value
° Cycle time for load is much longer than needed for all other instructions
Summary
° Single cycle datapath => CPI=1, CCT => long