Lecture 12

Finite State Machine Design

Prith Banerjee
ECE C03
Advanced Digital Design
Spring 1998

ECE C03 Lecture 12 1

 Outline
Review of sequential machine design
Moore/Mealy Machines
FSM Word Problems
Finite string recognizer
Traffic light controller
READING: Katz 8.1, 8.2, 8.4, 8.5, Dewey 9.1, 9.2

ECE C03 Lecture 12 2

 Concept of the State Machine
Computer Hardware = Datapath + Control

Qualifiers
Registers FSM generating sequences
Combinational Functional of control signals
Units (e.g., ALU) Instructs datapath what to
Busses do next
Control

Control "Puppeteer who pulls the

strings"
State

Qualifiers Control
and Signal
Inputs Outputs

"Puppet" Datapath

ECE C03 Lecture 12 3

 Example: Odd Parity Checker

Assert output whenever input bit stream has odd # of 1's

Reset Present State Input Next State Output

Even 0 Even 0
Even 0 Even 1 Odd 0
[0] Odd 0 Odd 1
Odd 1 Even 1
1 1 Symbolic State Transition Table
Odd
[1] Present State Input Next State Output
0
0 0 0 0
0 1 1 0
1 0 1 1
State 1 1 0 1
Diagram
Encoded State Transition Table

ECE C03 Lecture 12 4

 Odd Parity Checker Design
Next State/Output Functions
NS = PS xor PI; OUT = PS

Input Output
NS T Q
Input
D Q CLK
PS/Output
CLK Q
R
Q R
\Reset \Reset
D FF Implementation T FF Implementation

Input 1 0 0 1 1 0 1 0 1 1 1 0

Clk

Output 1 1 1 0 1 1 0 0 1 0 1 1

Timing Behavior: Input

ECE C03 1 0120 1 1 0 1 0 1 1 1 0
Lecture 5
 Timing of State Machines
When are inputs sampled, next state computed, outputs asserted?
State Time: Time between clocking events

Clocking event causes state/outputs to transition, based on inputs

For set-up/hold time considerations:

Inputs should be stable before clocking event

After propagation delay, Next State entered, Outputs are stable

NOTE: Asynchronous signals take effect immediately

Synchronous signals take effect at the next clocking event

E.g., tri-state enable: effective immediately

sync. counter clear: effective at next clock event

ECE C03 Lecture 12 6

 Timing of State Machine
Example: Positive Edge Triggered Synchronous System

State Time On rising edge, inputs sampled

outputs, next state computed

After propagation delay, outputs and

next state are stable
Clock
Immediate Outputs:
affect datapath immediately
Inputs could cause inputs from datapath to change

Delayed Outputs:
take effect on next clock edge
Outputs propagation delays must exceed hold times

ECE C03 Lecture 12 7

 Communicating State Machines
One machine's output is another machine's input
X

FSM 1 FSM 2
CLK
Y

FSM 1 A A B

Y=0 X=0
Y=0 X=0 X
A C
[1] [0]
FSM 2 C D D
X=1
Y=1
X=1 Y

B D
Y=0,1 [0] X=0 [1]

Machines advance in lock step

Initial inputs/outputs: X = 0, Y = 0
ECE C03 Lecture 12 8
 Basic Design Approach
1. Understand the statement of the Specification

2. Obtain an abstract specification of the FSM

3. Perform a state mininimization

4. Perform state assignment

5. Choose FF types to implement FSM state register

6. Implement the FSM

1, 2 covered now; 3, 4, 5 covered later;

4, 5 generalized from the counter design procedure

ECE C03 Lecture 12 9

 Example: Vending Machine FSM
General Machine Concept:
deliver package of gum after 15 cents deposited

single coin slot for dimes, nickels

no change

Step 1. Understand the problem:

Draw a picture!

Block Diagram N
Coin
Vending Open Gum
Sensor D
Machine Release
Reset FSM Mechanism

Clk

ECE C03 Lecture 12 10

 Vending Machine Example
Step 2. Map into more suitable abstract representation

Reset
S0

Tabulate typical input sequences:

N D
three nickels
nickel, dime S1 S2
dime, nickel
two dimes
two nickels, dime N D N
D

Draw state diagram: S3 S4 S5 S6

Inputs: N, D, reset [open] [open] [open]

N D
Output: open
S7 S8
[open] [open]

ECE C03 Lecture 12 11

 Vending Machine Example
Step 3: State Minimization

Present Inputs Next Output

Reset
0
State D N State Open
0 0 0 0 0
N
0 1 5 0
1 0 10 0
5
D 1 1 X X
5 0 0 5 0
N 0 1 10 0
10 1 0 15 0
D 1 1 X X
N, D
10 0 0 10 0
0 1 15 0
15
1 0 15 0
[open]
1 1 X X
15 X X 15 1
reuse states
whenever Symbolic State Table
possible

ECE C03 Lecture 12 12

 Vending Machine Example
Step 4: State Encoding
Present State Inputs Next State Output
Q1 Q0 D N D 1 D0 Open
0 0 0 0 0 0 0
0 1 0 1 0
1 0 1 0 0
1 1 X X X
0 1 0 0 0 1 0
0 1 1 0 0
1 0 1 1 0
1 1 X X X
1 0 0 0 1 0 0
0 1 1 1 0
1 0 1 1 0
1 1 X X X
1 1 0 0 1 1 1
0 1 1 1 1
1 0 1 1 1
1 1 X X X

ECE C03 Lecture 12 13

 Vending Machine Example
Step 5. Choose FFs for implementation D FF easiest to use
Q1 Q1 Q1
Q1 Q0 Q1 Q0 Q1 Q0
DN DN DN
0 0 1 1 0 1 1 0 0 0 1 0

0 1 1 1 1 0 1 1 0 0 1 0
N N N
X X X X X X X X X X X X
D D D
1 1 1 1 0 1 1 1 0 0 1 0
Q0 Q0 Q0
K-map for D1 K-map for D0 K-map for Open
Q1
D D1 Q1
D Q
CLK \ Q1
Q0
R
Q D1 = Q1 + D + Q0 N
N
\reset
N
\ Q0 OPEN D0 = N Q0 + Q0 N + Q1 N + Q1 D
Q0
\N
D0
D Q
Q0 OPEN = Q1 Q0
Q1 CLK \ Q0
N Q
R
8 Gates
Q1 \reset
D
ECE C03 Lecture 12 14
 Alternative State Machine
Representations
Why State Diagrams Are Not Enough
Not flexible enough for describing very complex finite state machines

Not suitable for gradual refinement of finite state machine

Do not obviously describe an algorithm: that is, well specified

sequence of actions based on input data

algorithm = sequencing + data manipulation

separation of control and data

Gradual shift towards program-like representations:

Algorithmic State Machine (ASM) Notation

Hardware Description Languages (e.g., VHDL)

ECE C03 Lecture 12 15

 Alternative State Machine
Representations
Algorithmic State Machine (ASM) Notation
Three Primitive Elements:

State Box

Decision Box State

Entry Path

Output Box State Code

* ***
State Machine in one state State State Box
block per state time Name
State ASM
Output List
Single Entry Point T F
Block
Condition

Unambiguous Exit Path

for each combination Condition Output
Box
of inputs Box
Conditional
Output List
Outputs asserted high (.H)
or low (.L); Immediate (I) Exits to
other ASM Blocks
or delayed til next clock
ECE C03 Lecture 12 16
 ASM Notation
Condition Boxes:
Ordering has no effect on final outcome

Equivalent ASM charts:

A exits to B on (I0 I1) else exit to C

A 010 A 010

F F
I0 I1
T T
F F
I1 I0

T T

B C B C
ECE C03 Lecture 12 17
 ASM Example: Parity Checker
Input X, Output Z
Even 0
Nothing in output list implies Z not asserted

Z asserted in State Odd

F
X Symbolic State Table:
T
Present Next
Input State State Output
Odd 1 F Even Even
H. Z T Even Odd
F Odd Odd A
T Odd Even A
F T
X
Encoded State Table:
Present Next
Input State State Output
Trace paths to derive 0 0 0 0
state transition tables 1 0 1 0
0 1 1 1
1 1 0 1
ECE C03 Lecture 12 18
ASM Chart: Vending Machine

0 00 10 10

T T
D D
F F
F F
N N
T T

5 01 15 11
H.Open

T F
N Reset
F T
F T
D 0
ECE C03 Lecture 12 19
 Moore and Mealy Machine Design
Procedure Moore Machine
Xi Zk
Combinational Outputs
Outputs are function
Inputs
Logic for solely of the current
Outputs and state
Next State
Outputs change
State synchronously with
State Register Feedback
Clock state changes

State
Register
Mealy Machine
Xi Comb.
Combinational
Inputs Logic for
Logic for
Outputs Outputs depend on
Next State state AND inputs
(Flip-flop Zk
Inputs) Outputs
Input change causes
Clock an immediate output
change
state Asynchronous signals
feedback
ECE C03 Lecture 12 20
 Equivalence of Moore and Mealy
Machines
Moore (N D + Reset)/0 N D + Reset
Reset/0 Reset
Mealy
Machine 0 0 Machine
[0]
Reset/0 Reset
N/0 N

5 5
N D/0 D/0 ND D
[0]

N/0 N

10 10
D/1 D
N D/0 [0] ND
N+D/1 N+D

15 15

[1] Reset
Reset/1

Outputs are associated Outputs are associated

with State with Transitions

ECE C03 Lecture 12 21

 States vs Transitions
Mealy Machine typically has fewer states than Moore Machine
for same output sequence
0
0 0/0
0

[0]
Same I/O behavior 0 1 0/0 1/0
0 1
1
Different # of states 1/1
[0]
1
2

[1] 1

S0 00 S0 0

IN IN

S1 01 S1 1
Equivalent
ASM Charts
IN IN

S2 10
H.OUT H.OUT

IN ECE C03 Lecture 12 22

Analyze Behavior of Moore Machines
Reverse engineer the following:

X J Q A Input X
C Output Z
X
KR Q \A State A, B = Z
\B
FFa
\Reset

Clk

X J Q Z
X C
KR Q \B
\A
FFb
\Reset
Two Techniques for Reverse Engineering:

Ad Hoc: Try input combinations to derive transition table

Formal: Derive transition by analyzing the circuit

ECE C03 Lecture 12 23
 Ad Hoc Reverse Engineering
Behavior in response to input sequence 1 0 1 0 1 0:
100

X
Clk
A
Z
\Reset
Reset X=1 X=0 X=1 X=0 X=1 X=0 X=0
AB = 00 AB = 00 AB = 11 AB = 11 AB = 10 AB = 10 AB = 01 AB = 00

A B X A+ B+ Z
0 0 0 ? ? 0
1 1 1 0
Partially Derived 0 1 0 0 0 1
1 ? ? 1
State Transition 1 0 0 1 0 0
Table 1 0 1 0
1 1 0 1 1 1
1 1 0 1
ECE C03 Lecture 12 24
 Formal Reverse Engineering
Derive transition table from next state and output combinational
functions presented to the flipflops!

Ja = X Ka = X B Z=B
Jb = X Kb = X xor A

FF excitation equations for J-K flipflop:

A+ = Ja A + Ka A = X A + (X + B) A
B+ = Jb B + Kb B = X B + (X A + X A) B

Next State K-Maps:

A+
State 00, Input 0 -> State 00
State 01, Input 1 -> State 01

B+

ECE C03 Lecture 12 25

Complete ASM Chart of Moore Machine

S0 00 S3 11
H.Z

0 1 0
X X
1
S1 01 S2 10
H.Z

0 1 1 0
X X

Note: All Outputs Associated With State Boxes

No Separate Output Boxes Intrinsic in Moore Machines

ECE C03 Lecture 12 26

 Behavior of Mealy Machines
Clk
\A
X
A B
D Q J Q
DA C
\A \B
C Q \X K Q
R R

\Reset \Reset

A
DA \X
X
B
B Z
\X X
A

Input X, Output Z, State A, B

State register consists of D FF and J-K FF
ECE C03 Lecture 12 27
 Ad Hoc Reverse Engineering
Signal Trace of Input Sequence 101011:
100

X Note glitches
Clk
in Z!
A Outputs valid at
B following falling
clock edge
Z
\Reset
Reset X =1 X =0 X =1 X =0 X =1 X =1
AB=00 AB=00 AB=00 AB=01 AB=11 AB=10 AB=01
Z =0 Z =0 Z =0 Z =0 Z=1 Z =1 Z =0

A B X A+ B+ Z
0 0 0 0 1 0
Partially completed 1 0 0 0
state transition table 0 1 0 ? ? ?
based on the signal 1 1 1 0
trace 1 0 0 ? ? ?
1 0 1 1
1 1 0 1 0 1
ECE C03 Lecture 121 ? ? ? 28
 Formal Reverse Engineering
A+ = B (A + X) = A B + B X

B+ = Jb B + Kb B = (A xor X) B + X B

=ABX + ABX + BX

Z =AX + BX
Missing Transitions and Outputs:
State 01, Input 0 -> State 01, Output 1
State 10, Input 0 -> State 00, Output 0
A+ State 11, Input 1 -> State 11, Output 1

B+

Z
ECE C03 Lecture 12 29
 ASM Chart of Mealy Machine
S0 = 00, S1 = 01, S2 = 10, S3 = 11

S0 00 S2 10

0
1 X
X
0 1
H. Z

H. Z S1 01 S3 11
H.Z

0 1 1
X X
0

NOTE: Some Outputs in Output Boxes as well as State Boxes

This is intrinsic in Mealy Machine implementation
ECE C03 Lecture 12 30
 Synchronous Mealy Machines
Clock

Xi Zk
Inputs Combinational
Outputs
Logic for
Outputs and
Next State

State Register Clock state

feedback

latched state AND outputs

avoids glitchy outputs!

ECE C03 Lecture 12 31
 Finite State Machine Word Problems

Mapping English Language Description to Formal Specifications

Case Studies:

Finite String Pattern Recognizer

Traffic Light Controller

We will use state diagrams and ASM Charts

ECE C03 Lecture 12 32

 Finite String Pattern Recognizer

A finite string recognizer has one input (X) and one output (Z).
The output is asserted whenever the input sequence 010
has been observed, as long as the sequence 100 has never been
seen.

Step 1. Understanding the problem statement

Sample input/output behavior:

X: 00101010010
Z: 00010101000

X: 11011010010
Z: 00000001000

ECE C03 Lecture 12 33

 Finite String Recognizer

Step 2. Draw State Diagrams/ASM Charts for the strings that must be
recognized. I.e., 010 and 100.
Reset
S0
[0] Moore State Diagram
Reset signal places
S1 S4 FSM in S0
[0] [0]

S2 S5
[0] [0]

S3 S6
Outputs 1 Loops in State
[1] [0]

ECE C03 Lecture 12 34

 Finite String Recognizer
Exit conditions from state S3: have recognized 010
if next input is 0 then have 0100!
if next input is 1 then have 0101 = 01 (state S2)

Reset
S0
[0]

S1 S4
[0] [0]

S2 S5
[0] [0]

S3 S6
[1] [0]

ECE C03 Lecture 12 35

 Finite String Recognizer
Exit conditions from S1: recognizes strings of form 0 (no 1 seen)
loop back to S1 if input is 0

Exit conditions from S4: recognizes strings of form 1 (no 0 seen)

loop back to S4 if input is 1

Reset
S0
[0]

S1 S4
[0] [0]

S2 S5
[0] [0]

S3 S6
[1] [0]
ECE C03 Lecture 12 36
 Finite String Recognizer
S2, S5 with incomplete transitions

S2 = 01; If next input is 1, then string could be prefix of (01)1(00)

S4 handles just this case!

S5 = 10; If next input is 1, then string could be prefix of (10)1(0)

S2 handles just this case!
Reset
S0
[0]

S1 S4
[0] [0] Final State Diagram

S2 S5
[0] [0]

S3 S6
[1] [0]
ECE C03 Lecture 12 37
 Review of Design Process
Write down sample inputs and outputs to understand specification

Write down sequences of states and transitions for the sequences

to be recognized

Add missing transitions; reuse states as much as possible

Verify I/O behavior of your state diagram to insure it functions

like the specification

ECE C03 Lecture 12 38

 Traffic Light Controller
A busy highway is intersected by a little used farmroad. Detectors
C sense the presence of cars waiting on the farmroad. With no car
on farmroad, light remain green in highway direction. If vehicle on
farmroad, highway lights go from Green to Yellow to Red, allowing
the farmroad lights to become green. These stay green only as long
as a farmroad car is detected but never longer than a set interval.
When these are met, farm lights transition from Green to Yellow to
Red, allowing highway to return to green. Even if farmroad vehicles
are waiting, highway gets at least a set interval as green.

Assume you have an interval timer that generates a short time pulse
(TS) and a long time pulse (TL) in response to a set (ST) signal. TS
is to be used for timing yellow lights and TL for green lights.

ECE C03 Lecture 12 39

 Traffic Light Controller
Picture of Highway/Farmroad Intersection:

Farmroad

C
HL
FL
Highway

Highway
FL
HL C

Farmroad

ECE C03 Lecture 12 40

 Traffic Light Controller
Tabulation of Inputs and Outputs:
Input Signal Description
reset place FSM in initial state
C detect vehicle on farmroad
TS short time interval expired
TL long time interval expired

Output Signal Description

HG, HY, HR assert green/yellow/red highway lights
FG, FY, FR assert green/yellow/red farmroad lights
ST start timing a short or long interval

Tabulation of Unique States: Some light configuration imply others

State Description
S0 Highway green (farmroad red)
S1 Highway yellow (farmroad red)
S2 Farmroad green (highway red)
S3 Farmroad yellow (highway red)

ECE C03 Lecture 12 41

 Traffic Light Controller
Refinement of ASM Chart:
Start with basic sequencing and outputs:

S0 S3
H.HG H.HR
H.FR H.FY

S1 S2
H.HY H.HR
H.FR H.FG

ECE C03 Lecture 12 42

 Traffic Light Controller
Determine Exit Conditions for S0:
Car waiting and Long Time Interval Expired- C TL

S0 S0
H.HG H.HG
H.FR H.FR

0 0
TL TL C

1 1
0
C H.ST
1

H.ST S1
H.HY
H.FR
S1
H.HY
H.FR

Equivalent ASM Chart Fragments

ECE C03 Lecture 12 43
 Traffic Light Controller
S1 to S2 Transition:
Set ST on exit from S0
Stay in S1 until TS asserted
Similar situation for S3 to S4 transition

S1 S2
H.HY H.ST H.HR
H.FR H.FG

0 1
TS

ECE C03 Lecture 12 44

 Traffic Light Controller
S2 Exit Condition: no car waiting OR long time interval expired

S0 S3
H.HG H.HR
H.FR H.ST H.FY

0 1 0
TL C TS

H.ST H.ST

S1 S2
H.HY H.ST H.HR
H.FR H.FG

0 1 0
TS TL + C
1

Complete ASM Chart forLecture

ECE C03 Traffic
12 Light Controller 45
 Traffic Light Controller
Compare with state diagram:
TL + C
Reset
S0: HG
S0
TLC/ST TS/ST S1: HY
TS
S2: FG
S1 S3

TS S3: FY
TS/ST
TL + C/ST
S2

TL C

Advantages of State Charts:

Concentrates on paths and conditions for exiting a state

Exit conditions built up incrementally, later combined into

single Boolean condition for exit

Easier to understand the

ECE C03 design
Lecture 12 as an algorithm 46
 Summary
Review of sequential machine design
Moore/Mealy Machines
FSM Word Problems
Finite string recognizer
Traffic light controller
NEXT LECTURE: Finite State Machine
Optimization
READING: Katz 9.1, 2.2.1, 9.2.2, Dewey 9.3

ECE C03 Lecture 12 47