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MEMORIES
Memory Classification
Memory Architectures
Periphery
Reliability
DRAM LIFO
Shift Register
CAM
AK
Row Decoder
AL-1
M.2K
A0
Column Decoder Selects appropriate
AK -1 word
Input-Output
(M bits)
Row
Address
Column
Address
Block
Address
I/O
Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings
Read Cycle
READ
WRITE
Write Access
Data Valid
DATA
Data Written
Address
Row Address Column Address
Bus
RAS Address
Address
Bus
Address transition
CAS initiates memory operation
RAS-CAS timing
WL[0]
GND
WL[1]
WL[2]
GND
WL[3]
WL[0]
GND (diffusion)
WL[1]
Polysilicon
Basic cell
10 x 7 Metal1
WL[2] 2
WL[3]
WL[0]
GND (diffusion)
Basic Cell
8.5 x 7
Metal1 over diffusion
WL[1]
Polysilicon
WL[2]
WL[3]
Pull-up devices
WL[0]
WL[1]
WL[2]
WL[3]
Polysilicon
Basic cell
5x 6
Threshold
lowering
implant
VDD
BL
rword
Model for NOR ROM WL
Cbit
cword
BL
CL
rbit
Model for NAND ROM
rword cbit
WL
cword
tword = 0.38 (rword cword ) M2 = 0.38 (35 (0.65 + 5.1) fF) 5122 = 20 nsec
Metal bypass
WL[0]
GND
WL[1]
WL[2]
GND
WL[3]
tox G
tox
S
+ p +
n n
Substrate
20 V 0V 5V
20 V 0V 5V
10 V 5 V 5 V 2.5 V
S D S D S D
20-30 nm 10 V VGD
10 V
n+ n+
Substrate
p
10 nm
WL
V DD
Control gate
Floating gate
n+ source n+ drain
programming
p-substrate
STATIC (SRAM)
Data stored as long as supply is applied
Large (6 transistors/cell)
Fast
Differential
DYNAMIC (DRAM)
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended
Digital Integrated Circuits Memory Prentice Hall 1995
6-transistor CMOS SRAM Cell
WL
VDD
M2 M4
Q
Q M6
M5
M1 M3
BL BL
VDD
M4
Q=0 M6
M5 Q=1
M1
VDD
BL = 1 BL = 0
VDD VDD 2
k n M6 VDD VTn ----------- ----------
VDD VDD 2
- = k p M4 VDD VTp ----------- ----------
- (W/L)n,M60.33 (W/L)p,M4
2 8 2 8
kn M5 V VDD 2 V DD V 2
-------------- ----------
DD
- V ----------
- = k V V ---------- DD
- ----------- (W/L)n,M5 10 (W/L)n,M1
2 2 Tn 2 n M1 DD Tn 2 8
VDD
BL M4
BL
Q= 0 M6
M5 Q=1
M1 V DD
V DD V DD
Cbit C bit
kn M5 V VD D 2 VDD V 2
--------------- -----------
DD- V -----------
- = k V V D D-
------------ -----------
2 2 Tn 2 n M1 D D Tn 2 8
M2 M4
VDD
Q Q
M1 M3
GND
M5 M6 WL
BL BL
VDD
RL RL
Q Q
M3 M4
BL M1 M2 BL
WWL WWL
RWL
RWL
X VDD -VT
X M3
M2
M1 VDD
BL1
CS
RWL
M3
M2
WWL
M1
M1 CS X GND VDD VT
VDD
BL
VDD/2 VDD /2
CBL sensing
(b) Layout
Cell Plate Si
Si Substrate
2nd Field Oxide
Decoders
Sense Amplifiers
Input/Output Buffers
(N)AND Decoder
NOR Decoder
WL3
WL 3 VDD
WL2
WL 2 VDD
WL 1 WL1
VDD
WL 0 WL0
V DD A0 A0 A1 A1 A0 A0 A1 A1
WL 1
WL 0
A1 A 0 A0 A1 A3 A2 A2 A3
S0
A0 2 input NOR decoder
S1
S2
A1
S3
D
Advantage: speed (tpd does not add to overall memory access time)
only 1 extra transistor in signal path
Disadvantage: large transistor count
Digital Integrated Circuits Memory Prentice Hall 1995
4-to-1 tree based column decoder
BL0 BL1 BL2 BL3
A0
A0
A1
A1
D
Number of devices drastically reduced
Delay increases quadratically with # of sections; prohibitive for large decoders
Solutions: buffers
progressive sizing
combination of tree and pass transistor approaches
large small
small
transition s.a.
input output
x M1 M2 x x x
BL BL
EQ
SE M5 SE
WLi
(b) Doubled-ended Current Mirror Amplifier
VDD
SRAM cell i
y y
Diff.
x Sense x x x
Amp
y y
D D SE
EQ
BL BL
VDD
SE
SE
WL
BL
x Diff. x
+
cell S.A. _ Vref
y y
EQ
R L1 L0 R0 R1 L
VDD
SE
BLL BLR
... ...
CS CS CS SE CS CS CS
dummy dummy
cell cell
6.0
4.0
V (Volt)
BL
2.0 BL
5.0
0.00 4.0 WL
1 2 3 4 5
V (Volt)
t (nsec) 3.0 SE
(a) reading a zero
2.0 EQ
6.0
1.0
0.00 1 2 3 4 5
4.0
V (Volt)
0.00 1 2 3 4 5
t (nsec)
(b) reading a one
Vcasc
WLC
WL
DELAY
A0 td
ATD ATD
DELAY
A1 td
...
DELAY
AN-1 td
EQ
BL CBL x y
... Sense
C C C C C C
EQ Amplifier
BL CBL x y
CWBL
BL
Ccross
BL
SA
BL
BL"
BL
Ccross
BL
SA
BL
BL"
-particle
WL
VDD
BL
SiO2
n+
Row
Address
Redundant
rows
Fuse
:
Bank
Redundant
columns
Row Decoder
Memory
Array
Column
Column Decoder
Address
Product Terms
x0x1
AND
x2 OR
PLANE PLANE
f0 f1
x0 x1 x2
VD D
GND GND GND GND
GND
GND
GND
VDD f0 f1
x0 x0 x1 x1 x2 x2
AND-PLANE OR-PLANE
GND VDD
OR
O R
AND
VDD f0 f1 GND
x0 x0 x1 x1 x2 x2
AND-PLANE OR-PLANE
AND
AND
AND OR
Dummy AND Row
OR
x0 x0 x1 x1 x2 x2 f0 f1
Pull-up devices Pull-up devices
Digital Integrated Circuits Memory Prentice Hall 1995
PLA versus ROM
IDENTICAL TO ROM!
Main difference
ROM: fully populated
PLA: one element per minterm