Flip Flops and Basic Flip Flops

based Systems
1

Mokhtar Nibouche
mokhtar.nibouche@uwe.ac.uk
Room 2N36
Department of Engineering Design and Mathematics
Faculty of Environment and Technology
University of the West of England
 Objectives
2

Upon Completion of this lecture, you should be able to:

Understand the operation of a flip flop
Differentiate between different types of flip flop
Differentiate between a flip flop and a latch
Determine the output of a flip flop in response to pulsed
inputs.
Understand the principle of a shift register
Understand the principle of frequency division (counting up
and down)
Draw pulsed waveforms to describe basic shift registers and
basic counters
 Introduction
3

In combinational circuits, the output levels at any

instant depends only on the levels of the inputs at
the same instant (e.g. output of a basic gate).
Any prior input level conditions have no impact on
the current output levels.
This is why combinational circuits have no memory.
Combinational circuits uses only logic gates as basic
building blocks.
 Introduction
4
In general, most digital systems have some sort of memory.

Combinational Memory
Outputs Outputs

Combinational Memory
Circuit Elements

Internal Feedback

External Inputs

A digital system is the combination of 2 distinct subsystems.

A combinational system.
A block of memory elements.
 Introduction
5

The basic memory element is called a Flip Flop.

A Flip Flop is made up of several gates, which are
connected in a specific manner.
The specific arrangement of the logic gates lead to a
digital system able to store information.
Asynchronous
Inputs Reset Q Normal Output
Set Flip
Clock
Input1 Flop
Synchronous Input2
Q Inverted Output
Inputs
 Clock Signal
6

Digital systems can operate either synchronously or

asynchronously.
In asynchronous systems, the output level change state at
any time in response to changes in the inputs levels.
These systems are more difficult to design.
In synchronous designs, the output will only change state
in response to an input signal called the clock signal.
A clock signal is rectangular pulse train.
The transitions or edges of a clock signal take place when
the signal state changes from 0 to 1 or from 1 to 0.
 Clock Signal
7

Rectangular
pulse train.
(a)

A transition from 0
to 1 is called a
positive transition
or rising edge. (b)

A transition from
1 to 0 is called a
negative transition
or negative edge.
(c)
 SR Flip Flop
8

S Q
Clk
R Q

Symbol of a SR flip flop triggered by the rising edge of the

clock (2 inputs: S and R; 2 outputs Q and NOT Q).
The flip flop changes states when a the clock input makes a
transition from 0 to 1 (synchronous).
The flip flop doesnt respond to any changes of the two
control inputs S and R until there is a transition of the clock
signal from 0 to 1.
 SR Flip Flop
9

S R Clk Q
0 0 Q0 (no Change)
0 1 0
1 0 1
1 1 (invalid)
The truth table (or transition table) shows how the SR flip
flop responds to the transition of the clock for all possible
combinations of the inputs S and R.
Q0 defines the state of Q prior to the transition of the clock.
The arrow defines the transition of the clock (positive
transition or rising edge). The arrow will also define
another possible transition of the clock (negative transition or
falling edge).
Clocked flip flops are also called edged-triggered flip flops.
 SR Flip Flop
10

Clk

No Clear or
Set Set
Change Reset

The waveform illustrates the operation of the SR flip flop.

The condition S = R = 1 shouldnt be used because of its
ambiguity.
 SR Flip Flop
11

S Q S R Clk Q
0 0 Q0 (no Change)
Clk
0 1 0
R Q 1 0 1
1 1 (invalid)

The symbol and truth table of a SR clocked flip flop that

responds to a clock transition from 1 to 0 (falling edge)
The truth table is exactly the same as for a SR flip flop that
responds to a positive transition.
 JK Flip Flop
12

J K Clk Q
J Q
0 0 Q0 (no Change)
Clk 0 1 0
1 0 1
K Q
1 1 Q 0 (toggle)

The symbol and truth table of a JK clocked flip flop that

responds to a clock transition from 0 to 1 (rising edge)
The inputs J and K control the state of the flip flop as the S
and R inputs do for a clocked SR flip flop.
The major difference between the SR flip flop and the JK flip
flop is that the last combination in the truth table (J = K =1) is
now defined. This is called the toggle state of the flip flop
(the flip flop will go to its opposite state).
 JK Flip Flop
13

J K Clk Q
J Q
0 0 Q0 (no Change)
Clk 0 1 0
K Q 1 0 1
1 1 Q 0 (toggle)

The symbol and truth table of a JK clocked flip flop that

responds to a clock transition from 1 to 0 (falling edge)
The truth table is exactly the same as for a JK flip flop that
responds to a positive transition.
It is clear that the JK flip flop is more versatile than a SR flip
flop as all the states are defined.
JK flip flops are widely used in binary counters
 JK Flip Flop
14

Clk

Clear or
Toggle No Set Toggle Toggle
Reset Change

The waveform illustrates the operation of the JK flip flop.

The condition J = K = 1 are defined (no ambiguity)
 D Flip Flop
15

D Q D Clk Q
Clk 0 0
1 1
Q

The symbol and truth table of a D clocked flip flop that

responds to a clock transition from 0 to 1 (rising edge)
Unlike the SR and JK flip flops, the D flip flop has only one
input.
The operation of D flip flop is very simple. At the rising edge
of the clock signal, the level of the input D is store in the flip
flop (Q = D).
Note that a falling edge triggered D flip flop will behave
exactly the same in response to a transition from 1 to 0.
 D Flip Flop
16

D J Q D Q
Clk Clk Clk
K Q Q

A D flip flop can be implemented using a JK flip flop.

This could be done by adding an inverter to the K input of
the JK flip flop, as illustrated in the figure.
 D Flip Flop
17

Clk

The waveform illustrates the operation of the D flip flop.

It is clear that Q is following D at the rising edge of the clock.
 D Flip Flop
18

PRN PRESET CLEAR Q

D Q
0 0 Not Used
Clk 0 1 Q=1
Q 1 0 Q=0
CLRN
1 1 No impact

All the flip flop that have been introduced had only synchronous
inputs (control inputs and clock).
However, most flip flops have at least one asynchronous input
that operate independently of synchronous inputs.
These asynchronous are used to force the flip flop to a HIGH state
(Q = 1) or to a LOW state (Q = 0). These two operations are called
SET and RESET.
A D flip flop has two asynchronous inputs PRN (PRESET) and
CLRN (CLEAR) that are active low.
 Setup Time of a Flip Flop
19

Two timing requirement must be met for a clocked

flip flop to respond reliably to its control inputs
during an active transition of the clock Setup Time
The Setup Time ts: the time
Synchronous interval that precedes the active
input transition of the clock signal
during which the control
synchronous input must be
Clock maintained at the proper level.
input
IC manufacturers usually
ts
specify the minimum allowed
setup time.
 Hold Time of a Flip Flop
20

Two timing requirement must be met for a clocked

flip flop to respond reliably to its control inputs
during an active transition of the clock Hold Time
The Hold Time tH: the time
Synchronous interval that immediately follows
input
the active transition of the clock
signal during which the
Clock
synchronous control input must be
input
maintained at the proper level.
tH IC manufacturers usually specify
the minimum allowed hold time.
 D Latch
21

D Q EN D Q
0 x Q0 (no Change)
1 0 0
En Q
1 1 1

The edge triggered or clocked flip flops uses an edge detector

circuit to ensure that changes take place only following an
active transition of the clock signal.
In case where this edge detector is not used, the resultant
circuit will operate in different manner.
EN is a asynchronous signal while in a edge triggered flip
flop, the clock is a synchronous signal.
The resulting circuit is called a latch.
 Shift Registers
22

Set

PRN Qa PRN Qb PRN Qc PRN Qd

D_in D Q D Q D Q D Q
Clk Clk Clk Clk

CLRN CLRN CLRN CLRN

Clear
Clock

4-bit shift right register using D flip flops with

asynchronous inputs PRN (PRESET) and CLRN
(CLEAR).
Once both Set and Clear are HIGH, the data at the input,
D_in, is shifted right in response to the rising edge of the
clock.
 4-bits Shift Register
23
8
Data

Clock

Q0
Output of the 1st FF
Q1
Output of the 2nd FF
Q2
Output of the 3rd FF
Q3
Output of the 4th FF
1 2 3 4 5 6 7
 Shift Registers
24

D_in

Clock

Set

Clear

Qa

Qb

Qc

Qd
 Frequency Division and Counting
25

'1' '1' '1'

Q0 Q1 Q2
J Q J Q J Q
Clk Clk Clk
K Q K Q K Q

Negative Edge triggered JK flip flops, where J = K =1.

Only the 1st flip flop is clocked.
The output of the 1st FF acts as the clock of the 2nd FF.
The output of the 2nd FF acts as the clock of the 3rd FF.
Leads to a frequency division at the output of the circuit by 22.
In general, for n flip flops frequency division by 2n-1.
 Frequency Division and Counting
26

Clock

Q2

Q1

Q0

000 001 010 011 100 101 110 111 000 001
It is clear from the waveform that each output of a flip flop,
the frequency is halved.
Very useful for circuits that requires different frequencies.
 Frequency Division and Counting
27

The sequential circuit is

22 21 20
dividing the frequency by a
Q2 Q1 Q0 power of 2, as well as
0 0 0 No transition yet
creating an ordered counting
After Transition 1
0 0 1 sequence.
0 1 0 After Transition 2
In this example, the counting
0 1 1 After Transition 3 is starting from 0 and ending
1 0 0 No transition yet at 7 (8 numbers).
1 0 1 After Transition 1
A counter that counts up to 7
1 1 0 After Transition 2 is called a modulo-8 counter
1 1 1 After Transition 3 or shortly a MOD-8 counter
(MOD-n for n numbers).
 Frequency Division and Counting
28

Q2 Q1 Q0 Each circle represents a

possible state the flip flops (the
000 number 010 represents the sate
010, where Q0 = 0, Q1 = 1 and
111 001 Q2 =0)
Looking at a particular state
circle will inform us about the
110 010
next and the previous states.
State transition diagram are
101 011 very useful in describing,
analysing and designing
100 counters and other sequential
State Transition Diagram circuits.
 Frequency Division and Counting
29

'1' '1' '1'

Q0 Q1 Q2
J Q J Q J Q
Clk Clk Clk
K Q K Q K Q

Negative Edge triggered JK flip flops, where J = K =1.

Only the 1st flip flop is clocked.
The inverted output of the 1st FF acts as the clock of the 2nd FF.
The inverted output of the 2nd FF acts as the clock of the 3rd FF.
Leads to a counting down process.
 Frequency Division and Counting
30

Clock

Q2

Q1

Q1

Q0

Q0

000 111 110 101 100 011 010 001 000 111
 Frequency Division and Counting
31

Q2 Q1 Q0 22 21 20
Q2 Q1 Q0
000
0 0 0
111 001 1 1 1
1 1 0
1 0 1
110 010 1 0 0
0 1 1
0 1 0
101 011 0 0 1

100 Counting Down

 Example
32
'1' '1' '1'

SET
Q0 SET
Q1 SET
Q2
J Q J Q J Q

K CLR Q K CLR Q K CLR Q

An asynchronous MOD-8 counting up circuit using

negative edge triggered JK flip flops is shown in figure
Q4, where a falling edge clock signal is applied to the
first JK flip flop only.
 Example
33

1. If the period of the clock signal is Tc = 0.2 ms, what is the

period of the clock signal at the input of the third flip flop?
What is then the period of the output signal Q2 of the same
flip flop? How many flip flops are required so that the clock
signal at the input of the last flip flop is 16 times of that at the
input of the first one?

2. The counter in the figure is used to implement a MOD-5

counter. Draw the state diagram of this MOD-5 counter and
its corresponding logic circuit.
 Example
34

1.
If Tc = 0.2 ms TQ1= 22x0.2 = 0.8ms
If Tc = 0.2 ms TQ2= 23x0.2 = 1.6ms
Tc = 16 x 0.2 = 24 x 0.2 5 flip flops are required
Q2 Q1 Q0

2.
000

'1' '1' '1'

111 001
Q0 Q1 Q2
SET SET SET
J Q J Q J Q
110 010

K CLR Q K CLR Q K CLR Q

101 011

100