Introduction to VHDL

MOKHTAR NIBOUCHE
MOKHTAR.NIBOUCHE@UWE.AC.UK
ROOM 2N36
DEPARTMENT OF ENGINEERING DESIGN AND
MATHEMATICS
FACULTY OF ENVIRONMENT AND TECHNOLOGY
UNIVERSITY OF THE WEST OF ENGLAND
 Learning Outcomes
2

At the end of this lecture you should be able to:

Understand the basic concepts of VHDL.
Write your first VHDL code (Structural).
 What is VHDL?
3

An acronym for Very high speed integrated circuit

Hardware Description Language
VHDL enables hardware modelling from gate to
system level
Allows various design methodologies (paradigms)
Provides technology independence
VHDL has been standardised:
VHDL 87
VHDL 93
VHDL 99
VHDL 08
 VHDL Paradigms
4

Basically, three different paradigms.

Behavioural (in terms of behaviour)

Data Flow (how the inputs and outputs of built
in primitive are connected together)
Structural (structure of the logic design)
 VHDL Paradigms
5

Behavioural (Functional)
The system in terms of its functionality
It does not contain any information about the
internal system structure.
It describes the expected behaviour: What a
system will do.
Response of outputs to inputs.
No clue as to HOW but describes WHAT a system
has to do.
 VHDL Paradigms
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Data Flow
How the inputs and outputs of built in
primitives are connected together.
It describes how signals (data) flow through the
logic circuit.
Mid ground between Behavioural and structural.
 VHDL Paradigms
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Structural
HOW a system is structured
what components should be used

describes internal structure of system

how these components should be connected

Similar to a textual version of a schematic

diagram
 Design Flow
8
1
Design Entry (VHDL)

Synthesis
Timing req met?
Functional Simulation

Prog. & Config

Design OK

Place and Route (Fitting)

Timing Simulation

1
 Describing a System in VHDL
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VHDL describes a system using three

sections :

An entity
An architecture

Packages
 The Entity
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A system communicates via an interface

Interface is entity in VHDL
Cannot have any VHDL system without an entity

entity entity_name is
generic (generic_list);
port (port_list);
end entity;
 The Architecture
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The body of the system accomplishes some

tasks on the data (e.g. data transformation)
In VHDL the body is called architecture

architecture architecture_name of entity_name is

Declarations;
Begin
Concurrent Statements;
end architecture;
 Packages
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External source of description

Allow you to define items outside of VHDL
standards
Must be declared in advance using library
and use keywords, usually before entity

library ieee;
use ieee.std_logic_1164.all;
 Example The Lift System
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library ieee; Packages

use ieee.std_logic_1164.all;
entity lift is Interface
port (B, S, R, C : in std_logic;
D : out std_logic);
end lift;
architecture gates of lift is Architecture
signal A, E: std_logic;
begin
A <= B AND NOT S;
E <= NOT (R XOR C);
D <= A AND E;
end gates
VHDL Implementation 1
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Data flow
Simulation 1
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 VHDL Implementation 2
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Using the truth table case signal_name is when statement.

Behavioural

Same Entity
Different architecture
Simulation 2
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 Communication
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A Port is a channel for dynamic communication

between a block and the environment.

The syntax of a port is : port (ports declaration)

Ports are mainly used in entities and components.

Five available ports in VHDL (consider only three):

in for an input port.
out for an output port.
inout for bidirectional port

A port could be a single line (wire) or a bus (vector).

 Communication
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Example 1: Declaration of ports in an entity

entity gate2 is entity multigate is
port (A,B : in std_logic; port (A,B : in std_logic_vector (3 downto 0);
C: out std_logic); C: out std_logic_vector (3 downto 0));
end gate2; end multigate;
Single line Bus vector

Example 2: Declaration of ports in a component

component gate2 component multigate
port (A,B : in std_logic; port (A,B : in std_logic_vector (3 downto 0);
C: out std_logic); C: out std_logic_vector (3 downto 0));
end gate2; end multigate;
Single line Bus vector
 Communication
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A signal is an internal channel for dynamic

communication between different parts of a logic design;
The syntax of a signal is: signal signal_name: signal type;
A signal is defined in declarative part of the architecture;
A signal is different from port;
A signal could be a single line (wire) or a bus (vector).

signal A,B : in std_logic;

Single line

signal A,B : in std_logic_vector (3 downto 0);

Bus vector
 The Process Statement
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Behavioural descriptions are supported with the

process statement.
The syntax of a process is:
process(sensitivity list)
Begin
---------;
end process;
The process statement can appear in the body of an
architecture.
Very important in sequential designs.
 Structural VHDL (Revisited)
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Describes
How a system is structured/Internal structure
of the system.
What components should be used.

How the components are connected

The basic building block is a component

A component needs to be:
Declared (one declaration)
Instantiated (multiple instances)
 Component Declaration
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The component declaration resembles the entity

declaration (replace entity by component)
Defines a component that is instantiated in the
architecture body.
A component is the basic building block in
structural VHDL

component component_name
generic (generic_list);
port (port_list);
end component;
 Component Declaration
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Comprises three parts

The component name

A generic clause (list of generics or parameters)

A port clause

Defined in the architecture body (declarative part)

component component_name
generic (generic_list);
port (port_list);
end component;
 Component Instantiation
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Comprises three parts

The component name

A generic map clause

A port map clause

Defined in the architecture body

Play the role played by architecture.

instantiation_label: component_name
generic map (generic_list)
port map (port_list) ;
 Component Example
26

Declaration: Takes place in the declarative part of the

architecture before begin.
component gate2 A1
gate2 D
port (A,B : in std_logic;
A2 S
C: out std_logic); gate2
A3
end gate2;

Instantiation: Takes place in the body of the

architecture after begin.
Inst 1: gate2 port map (A2,A3,S);
Inst 2: gate2 port map (A1,S,D);
 Example
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Consider the logic circuit below:

A2
A1 B2 Q
A0 B1
B0
C

Consists of three identical blocks (dotted white box) .

Possibility of block reuse (design or hardware reuse).
Create a VHDL component describing a block.
Use this component in a structural design (structural
VHDL)
 Example
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We need to describe one block using VHDL.

This block will be then saved as a component.
The names of the inputs and the inputs are not
important at this point (inputs: A, B and C,
output: Q).
The number of inputs and outputs is of
importance (3 inputs and 1 output).

A
B Q
C
VHDL Code Describing a Block
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Library

Entity

Architecture

A
B Q
C
 Component Declaration/Instantiation
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Component declaration
component lab4
port (a, b, c : in std_logic; Similar to the
q : out std_logic); entity declaration
end component;

Component Instantiation
inst1: lab4 port map (A(0), B(0), C, D(0)); Three instances
inst2: lab4 port map (A(1), B(1), D(0), D(1));
for three blocks
inst3: lab4 port map (A(2), B(2), D(1), Q);
 Signals to link Different Blocks
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A2
A1 B2 Q
A0 B1
B0 D1
C D0

Two signals D0 and D1

Using Components in VHDL Code
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Library

Entity

Component

Architecture
Declaration

Component
Instantiation