Combinational Logic Implementation

Two-level logic
Implementations of two-level logic
NAND/NOR
Multi-level logic
Factored forms
And-or-invert gates
Time behavior
Gate delays
Hazards
Regular logic
Multiplexers
Decoders
PAL/PLAs
ROMs
CS 150 - Fall 2000 - Combinational Implementation - 1
Implementations of Two-level Logic

Sum-of-products
AND gates to form product terms
(minterms)
OR gate to form sum

Product-of-sums
OR gates to form sum terms
(maxterms)
AND gates to form product

CS 150 - Fall 2000 - Combinational Implementation - 2

Two-level Logic using NAND Gates

Replace minterm AND gates with NAND gates

Place compensating inversion at inputs of OR gate

CS 150 - Fall 2000 - Combinational Implementation - 3

Two-level Logic using NAND Gates (contd)

OR gate with inverted inputs is a NAND gate

de Morgan's: A' + B' = (A B)'
Two-level NAND-NAND network
Inverted inputs are not counted
In a typical circuit, inversion is done once and signal
distributed

CS 150 - Fall 2000 - Combinational Implementation - 4

Two-level Logic using NOR Gates

Replace maxterm OR gates with NOR gates

Place compensating inversion at inputs of AND gate

CS 150 - Fall 2000 - Combinational Implementation - 5

Two-level Logic using NOR Gates (contd)

AND gate with inverted inputs is a NOR gate

de Morgan's: A' B' = (A + B)'
Two-level NOR-NOR network
Inverted inputs are not counted
In a typical circuit, inversion is done once and signal
distributed

CS 150 - Fall 2000 - Combinational Implementation - 6

Two-level Logic using NAND and NOR Gates

NAND-NAND and NOR-NOR networks

de Morgan's law: (A + B)'= A' B'
(A B)' = A' + B'
written differently: A + B = (A' B')
(A B) = (A' + B')'
In other words
OR is the same as NAND with complemented inputs
AND is the same as NOR with complemented inputs
NAND is the same as OR with complemented inputs
NOR is the same as AND with complemented inputs

OR OR AND AND

NAND NAND NOR NOR

CS 150 - Fall 2000 - Combinational Implementation - 7

Conversion Between Forms

Convert from networks of ANDs and ORs to networks

of NANDs and NORs
Introduce appropriate inversions ("bubbles")
Each introduced "bubble" must be matched by a
corresponding "bubble"
Conservation of inversions
Do not alter logic function
Example: AND/OR to NAND/NAND
A A
NAND
B B
Z NAND Z
C C
NAND
D D
CS 150 - Fall 2000 - Combinational Implementation - 8
Conversion Between Forms (contd)

Example: verify equivalence of two forms

A A
NAND
B B
Z NAND Z
C C
NAND
D D

Z = [ (A B)' (C D)' ]'

= [ (A' + B') (C' + D') ]'
= [ (A' + B')' + (C' + D')' ]
= (A B) + (C D)

CS 150 - Fall 2000 - Combinational Implementation - 9

Conversion Between Forms (contd)

Example: map AND/OR network to NOR/NOR network

A

B
Z
C
D
\A
A NOR NOR
\B
B
Z NOR Z
C
\C
D NOR NOR
\D

Step 1 Step 2
conserve conserve
"bubbles" "bubbles"
CS 150 - Fall 2000 - Combinational Implementation - 10
Conversion Between Forms (contd)

Example: verify equivalence of two forms

\A
A NOR
\B
B
Z
C NOR Z

D \C
NOR
\D

Z = { [ (A' + B')' + (C' + D')' ]' }'

={ (A' + B') (C' + D') }'
= (A' + B')' + (C' + D')'
= (A B) + (C D)

CS 150 - Fall 2000 - Combinational Implementation - 11

Multi-level Logic

x=ADF + AEF + BDF + BEF + CDF + CEF +

G
Reduced sum-of-products form already simplified
6 x 3-input AND gates + 1 x 7-input OR gate (may not exist!)
25 wires (19 literals plus 6 internal wires)
x = (A + B + C) (D + E) F + G
Factored form not written as two-level S-o-P
1 x 3-input OR gate, 2 x 2-input OR gates, 1 x 3-input AND gate
10 wires (7 literals plus 3 internal wires)
A
B
C
X
D
E
F
G
CS 150 - Fall 2000 - Combinational Implementation - 12
Conversion of Multi-level Logic to NAND Gates
Level 1 Level 2 Level 3 Level 4
F = A (B + C D) + B C' C
D
original F
B
AND-OR
A
network
B
\C

C
D
introduction and F
B
conservation of
A
bubbles
B
\C

C
redrawn in terms D
F
of conventional \B
NAND gates A
B
\C

CS 150 - Fall 2000 - Combinational Implementation - 13

Conversion of Multi-level Logic to NORs

Level 1 Level 2 Level 3 Level 4

F = A (B + C D) + B C' C
D
original F
AND-OR B
network A
B
\C
C

introduction and D
F
conservation of B
bubbles A
B
\C

\C
\D
redrawn in terms F
B
of conventional
\A
NOR gates
\B
C
CS 150 - Fall 2000 - Combinational Implementation - 14
Conversion Between Forms

Example

A A
(a) (b)
B F B F
C X C X
D D
original circuit add double bubbles at inputs

A
A X
(c) B F
C (d)
\X B F
\D C \X
\D
distribute bubbles
insert inverters to fix mismatches
some mismatches

CS 150 - Fall 2000 - Combinational Implementation - 15

AND-OR-Invert Gates

AOI function: three stages of logicAND, OR, Invert

Multiple gates "packaged" as a single circuit block

logical concept possible implementation

A A
B B
Z Z
C C
D D

AND OR Invert NAND NAND Invert

& &
2x2 AOI gate + 3x2 AOI gate +
symbol symbol
& &

CS 150 - Fall 2000 - Combinational Implementation - 16

Conversion to AOI Forms

General procedure to place in AOI form

Compute complement of the function in sum-of-products form
By grouping the 0s in the Karnaugh map
Example: XOR implementationA xor B = A' B + A B'
AOI form: F = (A' B' + A B)'

A
A'
&
0 1 B' + F
A
B 1 0 &
B

CS 150 - Fall 2000 - Combinational Implementation - 17

Examples of using AOI gates

Example:
A
F = B C' + A C' + A B
0 1 1 1
F' = A' B' + A' C + B' C
C 0 0 1 0
Implemented by 2-input 3-stack AOI gate
B

F = (A + B) (A + C') (B + C')
F' = (B' + C) (A' + C) (A' + B')
Implemented by 2-input 3-stack OAI gate
Example: 4-bit equality function
Z = (A0B0+A0'B0')(A1B1+A1'B1')(A2B2+A2'B2')(A3B3+A3'B3')

each implemented in a single 2x2 AOI gate

CS 150 - Fall 2000 - Combinational Implementation - 18
Examples of Using AOI Gates (contd)

Example: AOI implementation of 4-bit equality function

A0 high if A0 B0
&
B0 low if A0 = B0
+
&

A1 &
B1 conservation of bubbles
+
&
NOR Z
A2 &
B2 if all inputs are low
+
& then Ai = Bi, i=0,...,3
output Z is high
A3 &
B3 +
&

CS 150 - Fall 2000 - Combinational Implementation - 19

Summary for Multi-level Logic

Advantages
Circuits may be smaller
Gates have smaller fan-in
Circuits may be faster
Disadvantages
More difficult to design
Tools for optimization are not as good as for two-level
Analysis is more complex

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Time Behavior of Combinational Networks

Waveforms
Visualization of values carried on signal wires over time
Useful in explaining sequences of events (changes in value)
Simulation tools are used to create these waveforms
Input to the simulator includes gates and their connections
Input stimulus, that is, input signal waveforms
Some terms
Gate delaytime for change at input to cause change at output
Min delaytypical/nominal delaymax delay
Careful designers design for the worst case
Rise timetime for output to transition from low to high voltage
Fall timetime for output to transition from high to low voltage
Pulse widthtime an output stays high or low between changes
CS 150 - Fall 2000 - Combinational Implementation - 21
Momentary Changes in Outputs

Can be usefulpulse shaping circuits

Can be a problemincorrect circuit
operation (glitches/hazards)
A B C D
Example: pulse shaping circuit F

A' A = 0
delays matter
in function

D remains high for

three gate delays after F is not always 0
A changes from low to high pulse 3 gate-delays wide

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Oscillatory Behavior

Another pulse shaping circuit +

resistor
A B
open C
switch D

close switch

initially
open switch
undefined

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Hazards/Glitches

Hazards/glitches: unwanted switching at the outputs

Occur when different paths through circuit have different
propagation delays
As in pulse shaping circuits we just analyzed
Dangerous if logic causes an action while output is unstable
May need to guarantee absence of glitches

Usual solutions
1) Wait until signals are stable (by using a clock): preferable
(easiest to design when there is a clock synchronous design)
2) Design hazard-free circuits: sometimes necessary (clock not
used asynchronous design)

CS 150 - Fall 2000 - Combinational Implementation - 24

Types of Hazards

Static 1-hazard
1 1
Input change causes output to go from 1 to 0 to 1 0

Static 0-hazard 1
INput change causes output to go from 0 to 1 to 0 0 0

Dynamic hazards 1 1
Input change causes a double change 0 0
from 0 to 1 to 0 to 1 OR from 1 to 0 to 1 to 0

1 1
0 0
CS 150 - Fall 2000 - Combinational Implementation - 25
Static Hazards

Due to a literal and its complement momentarily taking

on the same value
Thru different paths with different delays and reconverging
May cause an output that should have stayed at the
same value to momentarily take on Athe wrong value
Example: multiplexer
A B
S
F
S

S'
B
F
S' hazard
static-0 hazard static-1 hazard
CS 150 - Fall 2000 - Combinational Implementation - 26
Dynamic Hazards

Due to the same versions of a literal taking on

opposite values
Thru different paths with different delays and reconverging
May cause an output that was to change value to
change 3 times instead of once
A
Example: C
A
F B1
3
2
B B2
1
B3
C
F

hazard
dynamic hazards
CS 150 - Fall 2000 - Combinational Implementation - 27
Making Connections

Direct point-to-point connections between gates

Wires we've seen so far
Route one of many inputs to a single output ---
multiplexer
Route a single input to one of many outputs ---
demultiplexer
control control

multiplexer demultiplexer 4x4 switch

CS 150 - Fall 2000 - Combinational Implementation - 28
Mux and Demux

Switch implementation of multiplexers and

demultiplexers
Can be composed to make arbitrary size switching networks
Used to implement multiple-source/multiple-destination
interconnections

A Y

B Z

A Y

B Z

CS 150 - Fall 2000 - Combinational Implementation - 29

Mux and Demux (cont'd)

Uses of multiplexers/demultiplexers in multi-point

connections
A0 A1 B0 B1

MUX Sa MUX Sb multiple input sources

A B

Sum

Ss DEMUX multiple output destinations

S0 S1

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Multiplexers/Selectors

Multiplexers/Selectors: general concept

2n data inputs, n control inputs (called "selects"), 1 output
Used to connect 2n points to a single point
Control signal pattern forms binary index of input connected
to output
A Z I1 I0 A Z
0 I0 0 0 0 0
Z = A' I0 + A I1 0 0 1 0
1 I1
0 1 0 1
0 1 1 0
1 0 0 0
functional form 1 0 1 1
logical form 1 1 0 1
1 1 1 1
two alternative forms
for a 2:1 Mux truth table

CS 150 - Fall 2000 - Combinational Implementation - 31

Multiplexers/Selectors (cont'd)

2:1 mux: Z = A' I0 + A I1

4:1 mux: Z = A' B' I0 + A' B I1 + A B' I2 + A B I3
8:1 mux: Z = A'B'C'I0 + A'B'CI1 + A'BC'I2 + A'BCI3 +
AB'C'I4 + AB'CI5 + ABC'I6 + ABCI7
2 n -1
In general, Z = k=0
(mkIk)
in minterm shorthand form for a 2n:1 Mux I0
I1
I2
I3 8:1
I0 I4 Z
mux
I1 4:1 I5
I0 2:1 I2 Z I6
Z mux
I1 mux I3 I7

A A B A B C
CS 150 - Fall 2000 - Combinational Implementation - 32
Gate Level Implementation of Muxes

2:1 mux

4:1 mux

CS 150 - Fall 2000 - Combinational Implementation - 33

Cascading Multiplexers

Large multiplexers implemented by cascading smaller ones

8:1
I0
I1 4:1 mux alternative
I2 mux implementation
I3 2:1
Z I0 2:1 8:1
mux I1
I4 mux mux
I5 4:1
I6 mux I2 2:1
I7 I3 mux
4:1
Z
I4 mux
B C A 2:1
I5 mux
control signals B and C simultaneously choose
one of I0, I1, I2, I3 and one of I4, I5, I6, I7 I6 2:1
I7 mux
control signal A chooses which of the
upper or lower mux's output to gate to Z
C A B
CS 150 - Fall 2000 - Combinational Implementation - 34
Multiplexers as General-purpose Logic

2n:1 multiplexer implements any function of n variables

With the variables used as control inputs and
Data inputs tied to 0 or 1
In essence, a lookup table
Example:
F(A,B,C) = m0 + m2 + m6 + m7
= A'B'C' + A'BC' + ABC' + ABC 1 0
= A'B'(C') + A'B(C') + AB'(0) + AB(1) 0 1
1 2
0 3
0 4 8:1 MUX F
0 5
1 6
1 7
S2 S1 S0

A B C
CS 150 - Fall 2000 - Combinational Implementation - 35
 Multiplexers as General-purpose Logic
(contd)

2n-1:1 mux can implement any function of n variables

With n-1 variables used as control inputs and
Data inputs tied to the last variable or its complement
Example:
F(A,B,C) = m0 + m2 + m6 + m7
= A'B'C' + A'BC' + ABC' + ABC
= A'B'(C') + A'B(C') + AB'(0) + AB(1)
1 0
0 1 A B C F
1 2 0 0 0 1 C'
0 0 1 0 C' 0
0 3 F
F 0 1 0 1 C' 1 4:1 MUX
0 4 8:1 MUX C'
0 1 1 0 0 2
0 5
1 0 0 0 1 3 S1 S0
1 6 0
1 7 1 0 1 0
S2 S1 S0 1 1 0 1 1 A B
1 1 1 1

A B C CS 150 - Fall 2000 - Combinational Implementation - 36

Multiplexers as General-purpose Logic
(contd)

Generalization
I0 I1 . . . In-1 In F
. . . . 0 0 0 1 1 four possible
n-1 mux control configurations
variables . . . . 1 0 1 0 1
of truth table rows
single mux data can be expressed
variable as a function of In
0 In In' 1

Example: F(A,B,C,D) implemented by an 8:1 MUX

1 0
A D 1
1 0 1 1 0 2
choose A,B,C as control variables 1 3
1 0 0 0 D 4 8:1 MUX
D D 5
multiplexer implementation D 6
1 1 0 1
D 7
C
S2 S1 S0
0 1 1 0
B
CS 150 - Fall 2000 - Combinational Implementation - 37 A B C
Demultiplexers/Decoders

Decoders/demultiplexers: general concept

Single data input, n control inputs, 2n outputs
Control inputs (called selects (S)) represent binary index of
output to which the input is connected
Data input usually called enable (G)

1:2 Decoder: 3:8 Decoder:

O0 = G S O0 = G S2 S1 S0
O1 = G S O1 = G S2 S1 S0
O2 = G S2 S1 S0
2:4 Decoder: O3 = G S2 S1 S0
O0 = G S1 S0 O4 = G S2 S1 S0
O1 = G S1 S0 O5 = G S2 S1 S0
O2 = G S1 S0 O6 = G S2 S1 S0
O3 = G S1 S0 O7 = G S2 S1 S0

CS 150 - Fall 2000 - Combinational Implementation - 38

Gate Level iImplementation of Demultiplexers

1:2 Decoders
active-high active-low
enable enable
G O0 \G O0
S S
O1 O1
2:4 Decoders
G \G
O0 O0
active-high active-low
enable O1 enable O1

O2 O2

O3 O3

S1 S0 S1 S0
CS 150 - Fall 2000 - Combinational Implementation - 39
Demultiplexers as General-purpose Logic

n:2n decoder implements any function of n variables

With the variables used as control inputs
Enable inputs tied to 1 and
Appropriate minterms summed to form the function

0 A'B'C'
1 A'B'C
2 A'BC' demultiplexer generates appropriate
3 A'BC minterm based on control signals
1 3:8 DEC 4 (it "decodes" control signals)
AB'C'
5 AB'C
6 ABC'
7 ABC
S2 S1 S0

A B C

CS 150 - Fall 2000 - Combinational Implementation - 40

Demultiplexers as General-purpose Logic (contd)

F1 = A' B C' D + A' B' C D + A B C D

F2 = A B C' D + A B C 0 A'B'C'D'
1 A'B'C'D
F3 = (A' + B' + C' + D') 2 A'B'CD' F1
3 A'B'CD
4 A'BC'D'
5 A'BC'D
6 A'BCD'
4:16 7 A'BCD
Enable DEC 8 AB'C'D' F2
9 AB'C'D
10 AB'CD'
11 AB'CD
12 ABC'D'
13 ABC'D
14 ABCD'
15 ABCD F3

A B C D
CS 150 - Fall 2000 - Combinational Implementation - 41
Cascading Decoders

5:32 decoder
0 A'B'C'D'E' 0
1x2:4 decoder 1 1
2 2 A'BC'DE'
4x3:8 decoders 3:8 DEC3 3:8 DEC 3
4 4
5 5
6 6
7 7
S2 S1 S0 S2 S1 S0
0
F 2:4 DEC 1
2
S1 S0 3
0 0 AB'C'D'E'
A B 1 1
2 2
3:8 DEC3 3:8 DEC 3
4 4
5 5
6 6
7 ABCDE 7 AB'CDE
S2 S1 S0 S2 S1 S0

C D E C D E

CS 150 - Fall 2000 - Combinational Implementation - 42

Programmable Logic Arrays

Pre-fabricated building block of many AND/OR gates

Actually NOR or NAND
Personalized" by making or breaking connections among gates
Programmable array block diagram for sum of products form

inputs

OR
AND
product array
array
terms

outputs

CS 150 - Fall 2000 - Combinational Implementation - 43

Enabling Concept

Shared product terms among outputs

F0 = A + B' C'
example: F1 = A C' + AB
F2 = B' C' + AB
F3 = B' C + A

input side:
personality matrix
1 = uncomplemented in term
0 = complemented in term
product inputs outputs = does not participate
term A B C F0 F1 F2 F3
AB 1 1 0 1 1 0 output side:
B'C 0 1 0 0 0 1 1 = term connected to output
AC' 1 0 0 1 0 0 0 = no connection to output
B'C' 0 0 1 0 1 0
reuse of terms
A 1 1 0 0 1

CS 150 - Fall 2000 - Combinational Implementation - 44

Before Programming

All possible connections available before "programming"

In reality, all AND and OR gates are NANDs

CS 150 - Fall 2000 - Combinational Implementation - 45

After Programming

Unwanted connections are "blown"

Fuse (normally connected, break unwanted ones)
aAnti-fuse (normally disconnected, make wanted connections)
A B C

AB

B'C

AC'

B'C'

F0 F1 F2 F3
CS 150 - Fall 2000 - Combinational Implementation - 46
Alternate Representation for High Fan-in
Structures

Short-hand notation--don't have to draw all the wires

Signifies a connection is present and perpendicular signal is
an input to gate
notation for implementing
F0 = A B + A' B'
F1 = C D' + C' D
A B C D

AB
A'B'
CD'
C'D

AB+A'B'
CD'+C'D
CS 150 - Fall 2000 - Combinational Implementation - 47
Programmable Logic Array Example

Multiple functions of A, B, C full decoder as for memory address

bits stored in memory
F1 = A B C A B C
F2 = A + B + C
A'B'C'
F3 = A' B' C'
A'B'C
F4 = A' + B' + C'
A'BC'
F5 = A xor B xor C
A'BC
F6 = A xnor B xnor C
AB'C'
A B C F1 F2 F3 F4 F5 F6
0 0 0 0 0 1 1 0 0 AB'C
0 0 1 0 1 0 1 1 1 ABC'
0 1 0 0 1 0 1 1 1
0 1 1 0 1 0 1 0 0 ABC
1 0 0 0 1 0 1 1 1
1 0 1 0 1 0 1 0 0
1 1 0 0 1 0 1 0 0
1 1 1 1 1 0 0 1 1 F1 F2 F3 F4 F5
F6
CS 150 - Fall 2000 - Combinational Implementation - 48
PALs and PLAs

Programmable logic array (PLA)

What we've seen so far
Unconstrained fully-general AND and OR arrays
Programmable array logic (PAL)
Constrained topology of the OR array
Innovation by Monolithic Memories
Faster and smaller OR plane

a given column of the OR array

has access to only a subset of
the possible product terms

CS 150 - Fall 2000 - Combinational Implementation - 49

PALs and PLAs: Design Example

BCD to Gray code converter

A B C D W X Y Z A A
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1 0 0 X 1 0 1 X 0
0 0 1 0 0 0 1 1 0 1 X 1 0 1 X 0
D D
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0 C 0 1 X X C 0 0 X X

0 1 0 1 1 1 1 0 0 1 X X 0 0 X X
0 1 1 0 1 0 1 0 B B
0 1 1 1 1 0 1 1
1 0 0 0 1 0 0 1 K-map for W K-map for X
1 0 0 1 1 0 0 0
1 0 1 A A
1 1 0 1 X 0 0 0 X 1

minimized functions: 0 1 X 0 1 0 X 0
D D
C 1 1 X X C 0 1 X X
W=A+BD+BC
1 1 X X 1 0 X X
X = B C'
Y=B+C B B
Z = A'B'C'D + B C D + A D' + B' C D'
K-map for Y K-map for Z
CS 150 - Fall 2000 - Combinational Implementation - 50
PALs and PLAs: Design Example (contd)

Code converter: programmed PLA

minimized functions:
A B C D
W=A+BD+BC
X = B C'
A Y=B+C
BD Z = A'B'C'D + B C D + A D' + B' C D'

BC
BC' not a particularly good
B candidate for PAL/PLA
implementation since no terms
C are shared among outputs
A'B'C'D
BCD

AD' however, much more compact

BCD' and regular implementation
when compared with discrete
AND and OR gates
W X Y Z
CS 150 - Fall 2000 - Combinational Implementation - 51
PALs and PLAs: Design Example (contd)
A B C D

Code converter: A
programmed PAL BD
BC
0
BC'
0
0
4 product terms
per each OR gate 0
B
C
0
0
A'B'C'D
BCD
AD'
B'CD'

W X Y Z
CS 150 - Fall 2000 - Combinational Implementation - 52
PALs and PLAs: Design Example (contd)

Code converter: NAND gate implementation

Loss or regularity, harder to understand
Harder to make changes

A
A B
C
B W D
D B
B C
C D Z
A
B \D
X \B
C C
\D

Y
B

CS 150 - Fall 2000 - Combinational Implementation - 53

PALs and PLAs: Another Design Example

A B C D
Magnitude comparator
A A A'B'C'D'

1 0 0 0 0 1 1 1 A'BC'D
0 1 0 0 1 0 1 1 ABCD
D D
C 0 0 1 0 C 1 1 0 1 AB'CD'
0 0 0 1 1 1 1 0
AC'
B B
A'C
K-map for EQ K-map for NE
B'D
BD'
A A
0 0 0 0 0 1 1 1 A'B'D

1 0 0 0 0 0 1 1 B'CD
D D
C 1 1 0 1 C 0 0 0 0 ABC
1 1 0 0 0 0 1 0 BC'D'
B B

K-map for LT K-map for GT

CS 150 - Fall 2000 - Combinational Implementation - 54 EQ NE LT GT
Read-only Memories

Two dimensional array of 1s and 0s word lines (only one

is active decoder is
Entry (row) is called a "word" just right for this)
Width of row = word-size
1 1 1 1
Index is called an "address"
Address is input n
2 -1
Selected word is output
i word[i] = 0011
decoder
j word[j] = 1010

0
internal organization
0 n-1
Address
bit lines (normally pulled to 1 through
resistor selectively connected to 0
by word line controlled switches)

CS 150 - Fall 2000 - Combinational Implementation - 55

ROMs and Combinational Logic

Combinational logic implementation (two-level

canonical form) using a ROM
F0 = A' B' C + A B' C' + A B' C
F1 = A' B' C + A' B C' + A B C
F2 = A' B' C' + A' B' C + A B' C'
F3 = A' B C + A B' C' + A B C'

A B C F0 F1 F2 F3
0 0 0 0 0 1 0 ROM
0 0 1 1 1 1 0 8 words x 4 bits/word
0 1 0 0 1 0 0
0 1 1 0 0 0 1
1 0 0 1 0 1 1
1 0 1 1 0 0 0
1 1 0 0 0 0 1 A B C F0F1F2F3
1 1 1 0 1 0 0 address outputs
truth table block diagram
CS 150 - Fall 2000 - Combinational Implementation - 56
ROM Structure

Similar to a PLA structure but with a fully decoded

AND array
Completely flexible OR array (unlike PAL)
n address lines

inputs

memory
decoder 2n word
array
lines
(2n words
by m bits)

outputs

m data lines
CS 150 - Fall 2000 - Combinational Implementation - 57
ROM vs. PLA

ROM approach advantageous when

Design time is short (no need to minimize output functions)
Most input combinations are needed (e.g., code converters)
Little sharing of product terms among output functions
ROM problems
Size doubles for each additional input
Can't exploit don't cares
PLA approach advantageous when
Design tools are available for multi-output minimization
There are relatively few unique minterm combinations
Many minterms are shared among the output functions
PAL problems
Constrained fan-ins on OR plane
CS 150 - Fall 2000 - Combinational Implementation - 58
Regular Logic Structures for Two-level Logic

ROM full AND plane, general OR plane

Cheap (high-volume component)
Can implement any function of n inputs
Medium speed
PAL programmable AND plane, fixed OR plane
Intermediate cost
Can implement functions limited by number of terms
High speed (only one programmable plane that is much smaller
than ROM's decoder)
PLA programmable AND and OR planes
Most expensive (most complex in design, need more
sophisticated tools)
Can implement any function up to a product term limit
Slow (two programmable planes)
CS 150 - Fall 2000 - Combinational Implementation - 59
Regular Logic Structures for Multi-level Logic

Difficult to devise a regular structure for arbitrary

connections between a large set of different types
of gates
Efficiency/speed concerns for such a structure
Xilinx field programmable gate arrays (FPGAs) are just such
programmable multi-level structures
Programmable multiplexers for wiring
Lookup tables for logic functions (programming fills in the table)
Multi-purpose cells (utilization is the big issue)

Use multiple levels of PALs/PLAs/ROMs

Output intermediate result
Make it an input to be used in further logic

CS 150 - Fall 2000 - Combinational Implementation - 60

Combinational Logic Implementation Summary

Multi-level Logic
Conversion to NAND-NAND and NOR-NOR networks
Transition from simple gates to more complex gate building
blocks
Reduced gate count, fan-ins, potentially faster
More levels, harder to design
Time Response in Combinational Networks
Gate delays and timing waveforms
Hazards/glitches (what they are and why they happen)
Regular Logic
Multiplexers/decoders
ROMs
PLAs/PALs
Advantages/disadvantages of each
CS 150 - Fall 2000 - Combinational Implementation - 61