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Full Custom
Gate Array
Standard Cell
Structured
4
Full Custom ASICs [1]
development from
scratch
complete control
over each layer
may include analog
circuitry
special tools
highly complex and
time consuming
allows highest
optimization
[1] https://en.wikipedia.org/wiki/Application-specific_integrated_circuit#Full-
custom_design 5
Gate array ASICs [2]
basic cells are
premanufactured
only connections
are needed
fabrication is done
much faster and
cheaper
standard tools and
component libraries
lower density and
performance
almost obsolete
[2] Clive Maxfiel, Bebop to the Boolean Boogie. An Unconventional Guide
to Electronics, 2nd Edition, Newnes, 2003 6
Standard cells ASICs [2]
standard cells are
predesigned
finding optimal
placement and
routing is needed
full fabrication cycle
standard tools and
component libraries
close to optimal
higher abstraction
IP cores
dominant technique
[2] Clive Maxfiel, Bebop to the Boolean Boogie. An Unconventional Guide
to Electronics, 2nd Edition, Newnes, 2003 7
Structured ASICs [3]
premanufactured
base tiles/modules
and RAMs, PLLs,
clock trees, etc.
only connections
are needed
fabrication is done
much faster and
cheaper
standard tools and
component libraries
lower performance
[3] Clive Maxfield. (2004) The Design Warrior's Guide to FPGAs, Academic
Press, Inc. Orlando, FL, USA 8
Programmable logic device technolgies
Simple
Programmable Logic Devices
(SPLDs)
PROM
PLA
PAL
etc.
Complex Programmable Logic
Devices (CPLDs)
Field
Programmable Gate Arrays
(FPGAs)
9
Simple programmable logic device [3]
Programmable logic array (PLA)
[4] CoolRunner-II CPLD Family Data Sheet, DS090 (v3.1). September 11,
2008 11
Field-programmable gate array (1)
FPGA is an integrated circuit that
contains (re)configurable blocks of logic
and (re)configurable interconnect.
Field-programmable means that
(re)configuration can be done “in field”
(even when device is already deployed)
FPGA development flow:
Design
Verification (functional and hardware)
Redesign (errors, change in specification)
Software development 12
Conceptual structure of an FPGA [5]
[3] Clive Maxfield. (2004) The Design Warrior's Guide to FPGAs, Academic
Press, Inc. Orlando, FL, USA 15
Three-input LookUp Table (LUT) (2)
16
Three-input LookUp Table (LUT) (3)
20
Designing Digital Systems
Digital Design entry:
Schematic
HDLs (VHDL, Verilog, SystemVerilog)
High-level synthesis (C, C++, SystemC)
Digital Design with HDLs:
Logic gate level
Register Transfer Level (RTL)
Use synthesizable SUBSET of HDL
Designer should “help” the tool:
Consider the technology
Employ recommended coding style
Be as specific and clear as possible 21
Designing with FPGAs
FPGAsare likely to benefit from logic
redundancy-based techniques:
pipelining, one-hot FSM state encoding,
resource duplication instead of sharing, etc.
Logic gate-based optimization are
likely to be inefficient for FPGAs
LUTs are used to implement combinational logic
Asynchronous design is generally
not suited for FPGAs
avoid use of latches, asynchronous structures,
combinational loops, etc. 22
IAY0600
Dmitri Mihhailov
Tallinn University of Technology
Digital Systems Design Labs Staff
Lecturer:
Alexander Sudnitson (associate professor)
aleksander.sudnitson@ttu.ee
ICT-503 (620 2255)
Lab Assistant:
Dmitri Mihhailov (research scientist)
dmitri.mihhailov@ttu.ee
ICT-505 (no phone)
Technical Assistant:
Artjem Rjabov (early stage research scientist)
artjom.rjabov@ttu.ee
ICT-512 (620 2265) 24
IAY0600 Digital Systems Design Labs (1)
Lab Room:
ICT-502AB (~ 30 working places)
ICT-405 (15 working places)
Lab PCs require the same password that is used
to access other computers in TUT network
Lab Time:
GROUP A
Wednesdays 16:00 - 17:30 (primary time)
ICT-502AB
GROUP B
Wednesdays 17:45 - 19:15 (reserve time)
ICT-405
25
IAY0600 Digital Systems Design Labs (2)
Lab Course webpage:
http://ati.ttu.ee/~alsu/
IAY0600l Digital Systems Design
(WORKSHOPS)
http://ati.ttu.ee/~alsu/IAY0600l.html
The target lab course:
LABS SET I (Xilinx FPGA-based)
FPGA boards:
Digilent Nexys-3 (Xilinx Spartan-6 FPGA)
used for labs 2-5
Digilent ZedBoard (Xilinx Zynq-7020 FPGA)
used for labs 5-10
replaced with Digilent Nexys-4 (Xilinx Artix-7 FPGA) 33
IAY0600
Dmitri Mihhailov
Tallinn University of Technology
Xilinx ISE Design Suite
Project Navigator is graphical interface
for project and design management
Project Navigator GUI:
Sources window (top left)
Processes window (middle left)
Workspace window (top right)
Console Message window (bottom)
Project Navigator tools:
PlanAhead
ISim
XPower Analyzer
iMPACT 35
Project Navigator GUI
36
Project Navigator Sources Window
1
2
1 Design views
Implementation
Simulation
2 Top-level module marker 37
Project Navigator Processes Window (1)
Synthesize process:
Performs logic synthesis (HDL constructs are
transformed to generic digital components)
View RTL and Technology Schematics
Check Syntax
Generate Post-Synthesis Simulation Model
40
Project Navigator Processes Window (3)
Simulation view:
Simulate design at different steps in design flow
Simulation process:
ISim tool
45
Xilinx ISim Simulator Tool
1 2
1 ISim Simulator windows:
Simulation Objects (no variables)
Instances and Processes
Waveform
2 Re-launch button 46
Project Navigator Workspace Window
1
1 Language Templates
2 Float Window
47
Project Navigator Console Window
Console views:
Console (shows all messages)
Errors (shows only error messages)
Warnings (shows only warning messages) 48
Nexys-3 FPGA Board (1) [6]
Nexys-3 FPGA board features:
Xilinx Spartan-6 XC6LX16-CS324-3
Total of 48Mbytes of external memory
10/100 Ethernet port
micro USB port for power and programming
micro USB UART port
Type-A USB host port
VGA port
Four Pmod and one VHDC GPIO connectors
Eight slide switches, five push buttons and eight
LEDs, four-digit seven-segment display
100MHz fixed-frequency oscillator
[6] Nexys 3 FPGA Board Reference Manual, Digilent Inc., April 11, 2016. 49
Nexys-3 FPGA Board (2) [6]
[6] Nexys 3 FPGA Board Reference Manual, Digilent Inc., April 11, 2016. 50