HIGH SPEED DIGITAL DRIVE

CIRCUIT FOR VISIBLE LIGHT

COMMUNICATION (VLC)
ECRB424 – PROJECT 2
SEMESTER 2 2017/2018
 ECRB424 – PROJECT 2
SEMESTER 2 2017/2018

 NAME : MUHAMAD FARIS BIN FAUZI

 STUDENT ID : EE096394
 PROGRAM : BACHELOR IN ELECTRICAL AND ELECTRONIC ENGINEERING
 SUPERVISOR : DR. AHMAD WAFI BIN MAHMOOD ZUHDI
 Examiner : PROF. DR. CHANDAN KUMAR CHAKRABARTY
Presentation Overview

Introduction
Flow chart of VLC system
Objective
Circuit consideration
Circuit design
Simulation of result
Conclusion
Introduction

 Visible Light Communication (VLC) is one of the potential wireless technology

that using illumination of light as a medium to transfer a data.
 For a high speed digital circuit drive, a lot of considerations need to be done for
designing this circuit drive. Examples, the selection of transistor, LED, resistor and
others.
Flow of Visible Light Communications System

Modulation Driver Sensor Demodulation

• Data feed from • Circuit drive as a • Receiver circuit • Decode back to
source transmitter with with photo binary for
LED diode streaming
 OBJECTIVE ACHIEVED

 Able to create specific circuit that have a stable current and voltage
 Solve the problem if fault incurred with some analysis
 Design the high speed digital drive circuit for Visible Light Communication(VLC)
 Simulate the output in the software
Digital circuit design consideration

For the switching application

- Push pull circuit (MOSFET)
Voltage supply (Vdd)
- 5 volts (requirement for MOSFET)
Source (input)
- Pulse signal
Light emitting diode (LED)
- LXHL BW02 (1nF capacitance)
Circuit design that can drive a large capacitance
- Stage Ratios (inverter chain)
Stage ratio

 Sizing for large capacitive load (how many stage).

 This is the solution for drive a large capacitive load.
 This stage ratio use to minimize the propagation delay of the circuit.
 The number of stage is depend on the capacitive load.

As a conclusion, for this circuit drive, it already enough to use only 2 stages
because the LED capacitance value is small. Let the speed limitation just depend on
the source data not to the circuit.
 Circuit design for digital drive

Vdd p-MOS

Output

Source

n-MOS
Simulation of Circuit Drive

The simulation result for circuit drive shown based on :

• DC analysis : use to know the operating point of the circuit.

• AC analysis : to show the electrical bandwidth of the drive.

• Transient analysis : able to see the output current of the circuit drive.

• Eye diagram analysis : as indicator of the quality of signal in high speed digital
transmission.(prove the speed limit of drive)
DC Analysis Graph
AC Analysis Graph
Transient Analysis Graph
Solution for proving the result

The max current = 390.498mA (magnitude 1)

The min current = 0mA
Half of the max current = 170.249mA (magnitude 0.5)

The equation to convert the current in dB

• 10 log (1) = 0 dB
• 10 log (0.5) = -3 dB

Substitute the value of max current and half current in equation

• I max ->10 log (390.498mA) = -4.67884 dB
• I half ->10 log (170.249mA) = -7.68914 dB
Max current graph
Half current graph
Conclusions

The simulation and calculation will be keep testing form time to time to
archive the objective in order to get high speed output for digital visible light
communication (VLC) drive circuit. The little adjustment of the MOSFET value will
improve the stability of output and be able to archive 20MegaHz.