Question 1:

List down the steps you would follow while floor planning your block. Explain briefly atleast 10 important guidelines you
would follow while placing memories.
Question 2 :
All inputs required to implement a design are given in below folder.
/PD2/assignments/assignment_week3
Use them and answer the following(You don’t have to invoke ICC tool to answer these questions)

1) Write a small script to find out cells with more than 4 pins in the std-cell RVT max library. Note the number of cells in
an A4 sheet
2) Draw the waveform of the dominant clock signal mentioned in the input files.
3) Get the name of the cell with least area in the std-cell RVT max library. Note down the name of the cell and its area in
the A4 sheet.
4) Note down the number of Input ports this design has
5) Assuming the width and height of the floorplan for this design are 300um each, report the number of M4 tracks this
floorplan would have in the preferred direction
6) What is the smallest possible cell width this design can have
7) ( leakage power of AND2X2_RVT @ FF/1.16V/125C) / ( leakage power of AND2X2_RVT @ FF/1.16V/m40C) = ????
Question 3 :
All inputs required to implement a design are given in below folder.
/PD2/assignments/assignment_week3
Use them and do the following using ICC tool

1) Import the design & all inputs required to do physical design into ICC. Give log file name as logs/yourname_log1 for this ICC session. Report the
following using suitable commands. Note the answers in an A4 sheet
a) Total cell area
b) Number of std cells in the design
c) Number of macros in the design
d) Number of IO ports in the design
e) Report the number of IO ports missing input drive constraints
f) Dump no wire load pre layout timing and save the report as pre_layout_timing.rpt
2) Save the milkyway database of your design with name as given below
Import_design as the cell name and your name as the lib name.
3) Now exit ICC
4) Now invoke ICC again and read back the design you saved in step 2. Give log file name as logs/yourname_log2 for this session.
5) Once you have loaded the design, create a floorplan such that
a) Utilization of the core area of the design is 30%
b) Die-to-core area equal to the 10X where X is the min-width of M3 layer
c) Let each side of the block be of same length
d) Place all input ports on left edge of the floorplanned design and change the placement status of the pins to fixed.
e) Place all output ports on right edge of the florrplanned design and change the placement status of the pins to fixed.
f) Place all macros following all macro placement guidelines and then cut rows
g) Dump the floorplan DEF and save it with name “yourname_floorplan.def”
h) Save this database with name as given below
floorplan as the cell name and your name as the lib name.
i) In the A4 size paper, write down the number of M3 tracks your floorplanned design has
6) Now exit ICC