Chapter 8 Sedra Smith

Chapter #8: Differential and
Multistage Amplifiers
from Microelectronic Circuits Text
by Sedra and Smith
Oxford Publishing
Oxford University Publishing

Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
Introduction
 IN THIS CHAPTER YOU WILL LEARN:

 The essence of the operation of the MOS and the bipolar
differential amplifiers: how they reject common-mode noise or
interference and amplify differential signals.
 The analysis and design of MOS and BJT differential amplifiers.
 Differential amplifier circuits of varying complexity; utilizing
passive resistive loads, current-source loads, and cascodes -
the building blocks studied in Chapter 7.
 An ingenious and highly popular differential-amplifier circuit
that utilizes a current-mirror load.
Introduction
 IN THIS CHAPTER YOU WILL LEARN:

 The structure, analysis, and design of amplifiers composed of
two or more stages in cascade. Two practical examples are
studied in detail: a two-stage CMOS op-amp and four-stage
bipolar op-amp.

Introduction
 The differential-pair of differential-amplifier configuration is

widely used in IC circuit design.
 One example is input stage of op-amp.
 Another example is emitter-coupled logic (ECL).
 Technology was invented in 1940’s for use in vacuum tubes – the
basic differential-amplifier configuration was later implemented
with discrete bipolar transistors.
 However, the configuration became most useful with invention of
modern transistor / MOS technologies.

8.1. The MOS
Differential Pair
 Figure 8.1: MOS differential-pair configuration.

 Two matched transistors (Q1 and Q2) joined and
biased by a constant current source I.
 FET’s should not enter triode region of operation.

8.1. The MOS
Differential Pair
Figure 8.1: The basic MOS differential-pair configuration.

8.1.1. Operation with a
Common-Mode Input
Voltage
 Consider case when two gate terminals are joined

together.
 Connected to a common-mode voltage (VCM).
 vG1 = vG2 = VCM
 Q1 and Q2 are matched.
 Current I will divide equally between the two transistors.
 ID1 = ID2 = I/2, VS = VCM – VGS
 where VGS is the gate-to-source voltage.
Common-Mode Input
Voltage I 1 W
(8.2)  kn VGS  Vt 
2
2 2 L
(8.3) VOV  VGS  Vt
 Equations (8.2) through I 1 W 2
(8.8) describe this (8.4)  kn VOV
2 2 L
system, if channel- I W
length modulation is (8.5) VOV 
kn L
neglected.
I
 Note specification of (8.6) vD1  vD2  VDD  RD
2
input common-mode I
(8.7) max VCM   Vt  VDD  RD
range (VCM). 2
(8.8) min VCM   VSS  VCS  Vt  VOV
Differential Input Voltage
 If vid is applied to Q1 and Q2 is grounded, following

conditions apply:
 vid = vGS1 – vGS2 > 0
 iD1 > iD2
 The opposite applies if Q2 is grounded etc.
 The differential pair responds to a difference-mode or
differential input signals.

Figure 8.4: The MOS differential pair
with a differential input signal vid
Differential Input Voltage applied.
1 W 
(8.9) I   kn   vGS 1  Vt 
2
2 L 
(8.9) vGS 1  Vt  2I / kn W / L 
(8.9) vGS 1  Vt  2VOV
(8.10) max  vid   VGS 1  v S
(8.10) max  vid   2VOV

Differential Input Voltage
 Two input terminals connected to a suitable dc voltage

VCM.
 Bias current I of a “perfectly” symmetrical differential
pair divides equally.
 Zero voltage differential between the two drains (collectors).
 To steer the current completely to one side of the pair, a
difference input voltage vid of at least 21/2VOV (4VT for
bipolar) is needed.

8.1.3. Large-Signal
Operation
 Objective is to derive expressions for drain current iD1

and iD2 in terms of differential signal vid = vG1 – vG2.
 Assumptions:
 Perfectly Matched
 Channel-length Modulation is Neglected
 Load Independence
 Saturation Region

8.1.3. Large-Signal
Operation
1 W
(8.11) iD1  kn  vGS 1  Vt 

2
 step #1: Expression drain 2 L

currents for Q1 and Q2. 1 W
(8.12) iD2  kn  vGS 2  Vt 
2
 step #2: Take the square roots 2 L

of both sides of both (8.11) 
and (8.12)
1 W
 step #3: Subtract (8.14) from (8.13) iD1  kn  vGS 1  Vt 
2 L
(8.15) and perform
1 W
appropriate substitution. (8.14) iD2  kn  vGS 2  Vt 
 step #4: Note the constant- 2 L
current bias constraint. 
(8.15) vGS 1  vGS 2  vG 1  vG 2  vid
8.1.3. Large-Signal
Operation
 step #5: Simplify (8.15). (8.17) iD1  iD 2  I

 step #6: Incorporate 
the constant-current 1 W
bias. (8.17) 2 iD1 iD2  I  kn vid2
2 L
 step #7: Solve (8.16) 
and (8.17) for the two 2
unknowns – iD1 and iD2. I  I   vid   vid /2 
(8.23) iD1      1   
 Refer to (8.23) and 2  VOV  2   VOV 
(8.24). 2
I  I   vid   vid /2 
(8.24) iD2      1   
2  VOV   2 V
 OV 
8.1.3. Large-Signal
Operation
Figure 8.6: Normalized plots of the currents in a MOSFET differential pair. Note that
VOV is the overdrive voltage at which Q1 and Q2 operate when conducting drain
currents equal to I/2, the equilibrium situation. Note that these graphs are
Microelectronic Circuits by Adel S.universal and
Sedra and Kenneth apply
C. Smith to any MOS differential pair
(0195323033)
8.1.3. Large-Signal
Operation
 Transfer characteristics of (8.23) small-signal approximation
and (8.24) are nonlinear. I  I  vid

(8.25) iD1    
 Linear amplification is desirable 2  VOV  2
and vid will be as small as I  I  vid
possible. (8.26) iD2    
2  VOV  2
 For a given value of VOV, the only  I  vid
option is to keep vid/2 much (8.27) id   
V
 OV  2
smaller than VOV.

8.1.3. Large-Signal
Operation
Figure 8.7: The linear range of operation of the MOS differential pair can be extended
byS. Sedra
Microelectronic Circuits by Adel operating
and Kenneth C.the
Smith transistor
(0195323033) at a higher value of VOV .
8.2. Small-Signal Operation
of the MOS Differential
Pair

1
(8.28) vG1  VCM  vid
8.2.1. Differential Gain 2
1
(8.29) vG 2  VCM  vid
2

 Two reasons single-ended 2ID 2(I /2) I
amplifiers are preferable: (8.30) gm   
VOV VOV VOV
 Insensitive to 
interference. vid
(8.31) vo1  gm RD
 Do not need bypass 2
coupling capacitors. vid
(8.32) vo2  gm RD
2

vod
(8.35) Ad   gm RD
Oxford University Publishing vid
1
(8.28) vG1  VCM  vid
8.2.1. Differential Gain 2
1
(8.29) vG 2  VCM  vid
2

 For MOS pair, each device 2ID 2(I /2) I
operates with drain current (8.30) gm   
VOV VOV VOV
I/2 and corresponding

overdrive voltage (VOV).
vid
 a=1 (8.31) vo1  gm RD
2
 MOS: gm = I/VOV vid
(8.32) vo2  gm RD
 BJT: gm = aI/2VT 2

 MOS: ro = |VA|/(I/2).
vod
(8.35) Ad   gm RD
Oxford University Publishing vid
8.2.1. Differential Gain
 vi1 = VCM + vid/2 and vi2 = VCM – vid/2 causes a virtual

signal ground to appear on the common-source
(common-emitter) connection
 Current in Q1 increases by gmvid/2 and the current in Q2
decreases by gmvid/2.
 Voltage signals of gm(RD||ro)vid/2 develop at the two
drains (collectors, with RD replaced by RC).

8.2.2. The Differential
Half-Circuit
 Figure 8.9 (right): The

equivalent differential half-
circuit of the differential
amplifier of Figure 8.8.
 Here Q1 is biased at I/2 and is
operating at VOV.
 This circuit may be used to
determine the differential
voltage gain of the differential
amplifier Ad = vod/vid.

8.2.3. The Differential
Amplifier with Current-
Source Loads
 To obtain higher gain, the passive resistances (RD) can be

replaced with current sources.
 Ad = gm1(ro1||ro3)
Figure 8.11: (a) Differential amplifier

with current-source loads formed by
Q3 and Q4. (b) Differential half-circuit
of the amplifier in (a).

8.2.4. Cascode
Differential Amplifier
 Gain can be increased via

cascode configuration –
discussed in Section 7.3.
 Ad = gm1(Ron||Rop)
 Ron = (gm3ro3)ro1
 Rop = (gm5ro5)ro7
Figure 8.12: (a) Cascode differential

amplifier; and (b) its differential half
circuit.
8.2.5. Common-Mode Gain
and Common-Mode i
(8.41) vicm   2iRSS
Rejection ratio (CMRR) gm

vicm
 Equation (8.43) describes (8.42) i 
1/ gm  2RSS
effect of common-mode
signal (vicm) on vo1 and 
vo2. RD
(8.43) vo1  vo2   vicm
1/ gm  2RSS

vicm RD
(8.44) vo1  vo2  
2RSS

(8.45) vod  vo2  vo1  0
and Common-Mode R
(8.46) vo1   D vicm
Rejection ratio (CMRR) 2RSS
RD 's are
mismatched
RD  RD
 When the output is taken (8.47) vo2   vicm
2RSS
single-ended, magnitude of

common-mode gain is
defined in (8.46) and RD
(8.48) vod  vo2  vo1 
vicm
(8.47). 2RSS
 Taking the output 
differentially results in the vod RD  RD  RD 
(8.49) Acm     
perfectly matched case, in vicm 2RSS  2RSS   RD 
zero Acm (infinite CMRR). 
Ad
(8.50) CMRR 
Acm
and Common-Mode R
(8.46) vo1   D vicm
Rejection ratio (CMRR) 2RSS
RD 's are
mismatched
RD  RD
 Mismatches between the (8.47) vo2   vicm
2RSS
two sides of the pair make

Acm finite even when the
output is taken RD
(8.48) vod  vo2  vo1 
vicm
differentially. 2RSS
 This is illustrated in 
(8.49). vod RD  RD  RD 
(8.49) Acm     
 Corresponding expressions vicm 2RSS  2RSS   RD 
apply for the bipolar pair. 
Ad
(8.50) CMRR 
Acm
8.3. The BJT
Differential Pair
 Figure 8.15 shows the basic

BJT differential-pair
configuration.
 It is similar to the MOSFET
circuit – composed of two
matched transistors biased by
a constant-current source –
and is modeled by many
similar expressions.
Figure 8.15: The basic BJT differential-

Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033) pair configuration.
Figure 8.16: Different modes of operation of the BJT differential pair: (a) the
differential pair with a common-mode input voltage VCM; (b) the differential
pair with a “large” differential input signal; (c) the differential pair with a large
8.3.1. Basic Operation differential input signal of polarity opposite to that in (b); (d) the differential
pair with a small differential input signal vi. Note that we have assumed the
bias current source I to be ideal.
 To see how the BJT differential

pair works, consider the first
case of the two bases joined
together and connected to a
common-mode voltage VCM.
 Illustrated in Figure 8.16.
 Since Q1 and Q2 are matched,
and assuming an ideal bias
current I with infinite output
resistance, this current will
flow equally through both
transistors. Oxford University Publishing
8.3.1. Basic Operation
Figure 8.16: Different modes
of operation of the BJT
differential pair: (a) the
differential pair with a
common-mode
To see howinput the BJT differential
voltage
VCMpair
; (b)works, consider
the differential pairthe first
casea of
with the differential
“large” two bases joined
input signal;
together and(c)connected
the to a
differential pair with a large
common-mode voltage VCM.
differential input signal of
 Illustrated
polarity opposite tointhat
Figure
in 8.16.
 (b); (d) the
Since Q1differential
and Q2 are pair
matched,
with a small differential input
andvassuming
signal .i Note that anwe ideal
have bias
currentthe
assumed I with
bias infinite
current output
resistance,
source I to bethis current will
ideal.
flow equally through both
transistors. Oxford University Publishing
8.3.2. Input Common-
Mode Range
 Refer to the circuit in Figure 8.16(a).

 The allowable range of VCM is determined at the upper end by Q1
and Q2 leaving the active mode and entering saturation.
 Equations (8.66) and (8.67) define the minimum and maximum
common-mode input voltages.
I
(8.66) max VCM   VC  0.4  VCC  a RC  0.4
2

(8.67) min VCM   VEE  VCS  VBE

Summary
 The differential-pair or differential-amplifier configuration is most

widely used building block in analog IC designs. The input stage of
every op-amp is a differential amplifier.
 There are two reasons for preferring differential to single-ended
amplifiers: 1) differential amplifiers are insensitive to interference
and 2) they do not need bypass and coupling capacitors.
 For a MOS (bipolar) pair biased by a current source I, each device
operates at a drain (collector, assuming a = 1) current of I/2 and a
corresponding overdrive voltage VOV (no analog in bipolar). Each
device has gm=1/VOV (aI/2VT for bipolar).

Summary
 With the two input terminals connected to a suitable dc voltage

VCM, the bias current I of a perfectly symmetrical differential pair
divides equally between the two transistors of the pair, resulting
in zero voltage difference between the two drains (collectors). To
steer the current completely to one side of the pair, a difference
input voltage vid of at least 21/2VOV is needed.
 Superimposing a differential input signal vid on the dc common-
mode input voltage VCM such that vI1 = VCM + vid/2 and vI2 = VCM –
vid/2 causes a virtual signal ground to appear on the common-
source (common-emitter) connection.

Summary
 The analysis of a differential amplifier to determine differential

gain, differential input resistance, frequency response of
differential gain, and so on is facilitated by employing the
differential half-circuit which is a common-source (common-
emitter) transistor biased at I/2.
 An input common-mode signal vicm gives rise to drain (collector)
voltage signals that are ideally equal and given by –vicm(RD/2RSS)[-
vicm(RC/2REE) for the bipolar pair], where RSS (REE) is the output
resistance of the current source that supplies the bias current I.

Summary
 While the input differential resistance Rid of the MOS pair is

infinite, that for the bipolar pair is only 2rp but can be increased to
2(b+1)(re+Re) by including resistances Re in the two emitters. The
latter action, however, lowers Ad.
 Mismatches between the two sides of a differential pair result in a
differential dc output voltage (Vo) even when the two input
terminals are tied together and connected to a dc voltage VCM.
This signifies the presence of an input offset voltage VOS = VO/Ad.
In a MOS pair, there are three main sources for VOS. Two exist for
the bipolar pair.


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Chapter 8 Sedra Smith

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Chapter #8: Differential and

Oxford University Publishing

 IN THIS CHAPTER YOU WILL LEARN:

 IN THIS CHAPTER YOU WILL LEARN:

Oxford University Publishing

 The differential-pair of differential-amplifier configuration is

Oxford University Publishing

 Figure 8.1: MOS differential-pair configuration.

Oxford University Publishing

Figure 8.1: The basic MOS differential-pair configuration.

 Consider case when two gate terminals are joined

 If vid is applied to Q1 and Q2 is grounded, following

Oxford University Publishing

Oxford University Publishing

 Two input terminals connected to a suitable dc voltage

Oxford University Publishing

 Objective is to derive expressions for drain current iD1

Oxford University Publishing

 step #1: Expression drain 2 L

 step #2: Take the square roots 2 L

 step #5: Simplify (8.15). (8.17) iD1  iD 2  I

 Transfer characteristics of (8.23) small-signal approximation

and (8.24) are nonlinear. I  I  vid

Oxford University Publishing

Oxford University Publishing

 vi1 = VCM + vid/2 and vi2 = VCM – vid/2 causes a virtual

Oxford University Publishing

 Figure 8.9 (right): The

Oxford University Publishing

 To obtain higher gain, the passive resistances (RD) can be

Figure 8.11: (a) Differential amplifier

Oxford University Publishing

 Gain can be increased via

Figure 8.12: (a) Cascode differential

 Figure 8.15 shows the basic

Figure 8.15: The basic BJT differential-

 To see how the BJT differential

 Refer to the circuit in Figure 8.16(a).

Oxford University Publishing

 The differential-pair or differential-amplifier configuration is most

Oxford University Publishing

 With the two input terminals connected to a suitable dc voltage

Oxford University Publishing

 The analysis of a differential amplifier to determine differential

Oxford University Publishing

 While the input differential resistance Rid of the MOS pair is

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