Chapter 3.

Advanced Hardware
Fundamentals

The various parts you will commonly find in an

embedded-system circuit

발표일시 : 2003. 12. 29

발표자 : 채화영
 Contents
 3.1 Microprocessors
 3.2 Buses
 3.3 Direct Memory Access
 3.4 Interrupts
 3.5 Other Common Parts
 3.6 Built-Ins on the Microprocessor
 3.7 A Last Word about Hardware
 3.1 Microprocessors
 Address S ignal
 Data S ignal
A0 D0
A1 D1

 R E AD/
A2 D2

 Pulses low when it

An Dn want to get data

CLOCK1
 WR ITE /
CLOCK2  Pulses low when it
want to write data
 Clock S ignal Input
Fig. 3.1 A Very Basic Microprocessor
 3.1 Microprocessors(cont.)
 Microprocessor and microcontroller
 Microprocessor =
small and slow microprocessor
+ limited or no capability for using RAM and ROM
+ pins
( pins can be set high or low or sensed directly by
software)

→ There’s just small difference between them

 3.2 Buses
• Microprocessor can address 64K
A0 D0
of memory
A0 D0
A1 D1

• The size of ROM and RAM : 32K

A1 D1
A2 D2
A2 D2
... ...

• RE AD/ - OE/ (Output enable)

... ...
ROM
D7
A15 D7
CPU

• WRITE/ - WE/
A14

CE/
OE/

Clock
READ/
A15
• Address Bus
circuit

A0
A1
D1
D2
- Group of address signals
A2

WRITE/ RAM
• Data Bus
... ...

A14
D7
- Group of data signals
WE/
OE/

CE/

• A15 signals
- Decide which of two chips-
ROM or ROM
A15

Fig 3.2 A Very Basic Microprocessor System

 3.2 Buses(cont.)
 E xample
 Microprocessor tries to read from address
0x9123 1001 0001 0010 0011

A15 : 1 → ROM : high, disabled

RAM : low(inverter), enabled

RAM sees only

0x1123 001 0001 0010 0011
 3.2 Buses(cont.)
 Additional Devices on the Bus
 Microprocessor should share same bus with additional
devices
 Memory mapping : the device look like more
memory to the microprocessor
 Two address space was supported (Memory and
I/O address space)

I/O Selected chip

Low Memory address
space
high I/O address
space
 3.2 Buses(cont.)
A19
MEMEN/
A0 D0
A1 D1
A2 D2 These signal go
To the ROM and
RAM, as before
...
...
CPU
D7

A15

I/O A19 E nabled Address Range

I/O

READ/

WRITE/
device
low low MEMEN/ 0x00000-0x7ffff
high High DV1 0x80000-0x800ff
Low High DV2 0x80000-0x80007
D0
A0 D0 A0
D1
A1 D1 A1
...

D2
A2 D2 A2

DV1 DV2 ...

... ...

D7
A7 D7
WE/

WE/
OE/

OE/
CE/

CE/

A19 A19

Fig 3.4 Memory Mapping and the I/O Address Space

 3.2 Buses(cont.)
 Bus Handshaking
1. No Handshaking
 E ngineer must select parts for the circuit that can
keep up with the microprocessor
 Buy a microprocessor that is slow enough that it won’t
get ahead of the other parts
 3.2 Buses(cont.)
2. Wait Signals
Normal bus cycle

• This signal is that

A0-An

the memory can

D0-Dn

use to extend the READ/

bus cycle as needed.

• Need to build the
WAIT

Bus cycle extended by asserting the WAIT signal

circuitry to drive A0-An

the wait signal

correctly – time
D0-Dn

and cost problem READ/

WAIT

The device can assert the WAIT signal as long as

it needs to, and microprocessor will wait

Fig 3.5 Bus Handshaking with a Wait Signal

 3.2 Buses(cont.)
3. Wait State (and Performance)
• Wait State Generator is responsible for it
• Use different numbers of wait states for different parts of
the address space
- Microprocessor can handle with various devices in
the
system
 3.2 Buses(cont.)

T1 T2 Tw T3
Clock

A0-An

D0-Dn

READ/

Microprocessor Microprocessor Microprocessor Start of the

Drives address Drives READ low Reads th data Next bus cycle.
bus to start From the bus.
The bus cycle.

Fig 3.6 The Microprocessor Clock Times the Bus

 3.3 Direct Memory Access
DMA(Direct Memory Access)
 all without software assistance and the associated
overhead

Two Problem
1. DMA can’t drive address and data signal at the same
time as the microprocessor is driving those signals
2. How does the DMA know when it should transfer a
second byte?

WRITE

I/O RE AD Memory
 3.3 Direct Memory Access(cont.)
 Problem 1
Address bus, READ/ and WRITE/
DMAREQ

DMAACK
Micro
RAM
Processor

Data bus BUSREQ

BUSACK

BUSREQ BUSACK

WRITE/

Address
Address driven by DMA
DMA I/O
DMAACK
Data

DMAREQ Data driven by I/O device

Fig3.8 Architecture of a System with DMA Fig 3.9 DMA Timing

 3.3 Direct Memory Access(cont.)
 Problem2
1. E dge trigger: DMA will transfer a byte whenever it
sees a rising edge on DMARE Q
2. level trigger : DMA will transfer bytes as long as
DMARE Q remains high
 3.3 Direct Memory Access(cont.)
 Alternative way to make DMA work
Address bus, READ/ and WRITE/
DMAREQ

BUSREQ

Micro
RAM
Processor

Data bus BUSACK

WRITE/
BUSREQ BUSACK

READ/

I/O device drives DMA drives

The data bus. the data bus
Address

DMA I/O

Data

DMAREQ DMA drive I/O device DMA drives memory

Address on the bus Device addresss on the bus

Fig3.10 Architecture of a System with DMA Fig 3.11 DMA Timing

 3.4 Interrupts
 Interrupt
 it is told to stop doing what it is doing and execute
interrupt routine.

 IR Q(Interrupt R equest)
 The signal tells the microprocessor that it is time to
run the interrupt routine
 3.4 Interrupts(cont.)

I/O A

I/O B

I/O C
CPU

I/O D

IRQ0/
IRQ1/
IRQ2

Fig 3.12 Interrupt Connections

 3.5 Other Common Parts
 Universal Asynchronous R eceiver/Transmitter
and R S -232
 Convert data to and from a serial interface
 Microprocessor → some more memory, need
external circuitry for CE/ of UART
 Run at odd rates : 14.7456 MHz
 TXD, RXD, RTS (R equest To Send), CTS (Clear To
S end)
3.5 Other Common Parts(cont.)
 Registers
 Used to control UART, to send data to and to received
from UART
 Register for write bytes
 Receiving bytes
 Indicating error condition on received characters
 Telling The UART when to interrupt
3.5 Other Common Parts(cont.)

A0
A1
A2
Driver/
Receiver
D0
D1
D2 UART

D7 Connector

IRQ/

WE/
OE/

Clock
circuit

Fig 3.13 A System with a UART

 3.5 Other Common Parts(cont.)
 Programmable Array Logic
 Build more or less any small glue circuit you want
 Have 10 to 20 pins and array of gates called
PALs(Programmable Array Logic)
3.5 Other Common Parts(cont.)
Data, address, READ/, and WRITE/

CPU RAM

A15
A14

UART
RAMCE/

CLK

PAL ROM

UARTCE/

WAIT ROMCE/

Fig 3.14 A Circuit with a PAL In It

 3.5 Other Common Parts(cont.)
Declarations // declare a device name
AddrDecode DEVICE 'P22V10'

"INPUTS “ // declare input port

A15 PIN 1
A14 PIN 2
iClk PIN 3

"OUTPUT“ // declare output port

!RamCe PIN 19
!UartCe PIN 18
!RomCe PIN 17
Wait PIN 16
Wait2 PIN 15

Equations // conditions of enabling chips

RamCe = A15
RomCe = !A15 * !A14
UartCe = !A15 * A14

Wait.CLK = iClk // be evaluated when the rising edge of iClk

Wait2.CLK = iClk

Wait := (RomCe + UartCe) * !Wait2 // output signal change as soon as input signals change
Wait2 := Wait * !Wait2

end AddrDeode
 3.5 Other Common Parts(cont.)
Wait := (RomCe + UartCe) * !Wait2
Wait2 := Wait * !Wait2
iClk

A15

A14

RomCe/

Wait

Wait2

RomCe/ changs
immediately when
A14 and A15 change.
Wait and Wait2 changes only
On rising edges of iClk.

Fig 3.16 PAL Timing

 3.5 Other Common Parts(cont.)
 AS ICs(Application-S pecific Integrated Circuits)
 Microprocessor core + peripherals + glue circuitry

 FPGAs(Field-Programmable Gate Arrays):

 A large number of gates + connections
 3.5 Other Common Parts(cont.)
 Watchdog Timers
 Contains a timer that expires after a certain interval
unless it is restarted.
 If the timer is expire, the presumptions is that software
failed to restart it
 Generate RE S E T/ signal and send it to microprocessor
3.5 Other Common Parts(cont.)

Glue
circuit
Microprocessor

RESET/
Watchdog

RESET/ RESTART

Fig 3.18 Typical Use of a Watchdog Timer

 3.6 Built-Ins on the Microprocessor
 E ach auxiliary circuit is controlled by writing
values to a small collection of registers
 Timer
 A counter that counts the number of microprocessor
clock cycles
 Then cause an interrupt when the count expires

 DMA
 Since a DMA channel and the microprocessor
contend for the bus, certain process are simplified
 3.6 Built-Ins on the
Microprocessor(cont.)
 I/O pins
 Used for any number of purposes
 Turning LE Ds on or off
 Resetting a watchdog timer
 Reading from a one-pin or two-pin E E PR OM

 Address Decoding
 A handful of chip enable output pins that can be
connected directly to the other chips
 Memory Caches and Instruction Pipelines
 Caches : small, extremely fast memory
 Instruction Pipelines : a kind of caches for instruction.
3.6 Built-Ins on the Microprocessor(cont.)

EEROM EECLK
EEDATA

I/OA0
I/OA1
EEENABLE/
I/OA2
I/OA3
EEWRITE/
I/OB0
I/OB1
GREEN0
I/OB2
RED GREEN1
I/OB3

Watchdog

RESTART

Fig 3.19 Uses for I/O Pins

 3.7 A Last Word about Hardware
 Cost
 every copy of the hardware costs money- endeavor
to eliminate a tiny parts
 S pace
 portable, wearable, concealable
 Power
 more power -> a larger power supply
 Heat
 every additional part -> additional heat
 Fast
 clever software is better way