Professional Documents
Culture Documents
by John Skroder
Introduction
What is a microcontroller and how is it different
from a microprocessor?
A microcontroller is actually a microcomputer on a
single piece of silicon. It incorporates a
microprocessor as a key element.
Internal C
Data Bus Internal
Address
Bus
M68HC11 ADDRESSING MODES
Clear:
CLR – write $00 to a memory location
CLRA – change ACCA’s contents to $00
CLRB - change ACCB’s contents to $00
BCLR(Bit Clear) & BSET(Bit Set) instructions are used to clear or set
selected bits in a memory location. A mask byte is provided with
these instructions. The mask byte specifies which individual bits to
set or clear. For example to clear 0, 2, 4,and 6th bits of a memory
location the mask byte will be $55(%01010101). Similarly 1’s in the
BSET mask byte specify memory bits to be set.
BSET and BCLR instructions use direct or indexed mode
Eg: assume X = $0100
Address 010C contains $ CC
To change the contents of location $010C to $44, we use
BCLR C,X,$88
Shift, Rotate and Logic Instructions:
• Arithmetic shift left instructions start with ASL and logical shift left
instructions start with LSL. These instructions shift target’s MS bit
into the C flag.
• ASL/LSL – shift a memory byte left – indexed or extended mode
• ASLA/LSLA – shift ACCA left. – inherent mode
• ASLB/LSLB -- shift ACCB left. – inherent mode
• ASLD/LSLD -- shift the D register left. – inherent mode
• Both arithmetic and logic shift right instructions shift the target’s LS bit
into the C flag
• ROLA – rotate ACCA bits left
• RORA -- rotate ACCA bits right
• ROLB – rotate ACCB bits left
• RORB – rotate ACCB bits left
All these inherent mode
• ROL – rotate memory left
• ROR – rotate memory right
These two indexed or extended
• A rotate right instruction shifts target’s LS bit into the C flag and the
C flag into the target’s MS bit and bits 7 through 1 one place right
• A rotate left instruction shifts target’s MS bit into the C flag and the C
flag into the target’s LS bit and bits 7 through 1 one place left
• Two types in logic instructions
Add instructions:
• ABA – add the contents of ACCA to the contents of ACCB. Return 8
bit sum to ACCA. -- Inherent mode
• ADDA – ACCA ACCA + Memory. -- Immediate,direct,indexed or
extended mode
• ADDB – ACCB ACCB + Memory. -- Immediate,direct,indexed or
extended mode
• ADDD – ACCD ACCD + Memory. -- Immediate,direct,indexed or
extended mode, Add the conents of 2 memory locations (2 bytes) to
D register and return the result to D register.
• Eg: ADDD 3 – adds the contents of $0004 to the D register’s LS
byte and adds with carry the contents of $003 to the D register’s MS
byte and then returns the sum to the D register
• ADCA – ACCA C + ACCA + Memory -- Immediate,direct,indexed
or extended mode
• ADCB -- ACCB C + ACCB + Memory -- Immediate,direct,indexed
or extended mode
Subtraction instructions:
Multiply instructions:
• MUL – multiplies the contents of two accumulators and returns the
product to the D register. Uses inherent mode.
Division instructions:
• IDIV – integer divide.
• FDIV – fractional divide.
Both of these divide the D register by X register and return 16 bit quotient
to the X register and 16 bit reminder to the D register. Use inherent
mode.
Difference between IDIV and FDIV:
• IDIV is used to divide whole integers. FDIV is used to carry the
quotient to the right of radix point.
• Eg: $nnnn/$dddd=$qqqq.f(h)f(h)f(h)f(h)f(l)f(l)f(l)f(l)
Where $nnnn = a 16 bit numerator
$dddd = a 16 bit dinominator
$qqqq = the 16 bit integer quotient
f(h)f(h)f(h)f(h)f(l)f(l)f(l)f(l) = the 32 bit fractional quotient
Use IDIV and FDIV to solve the problem as follows:
The M68HC11 can test the contents of ACCA or ACCB and set or reset
the CCR’s N and Z flags accordingly.
• TSTA – test ACCA’s contents to zero or minus
• TSTB -- test ACCB’s contents to zero or minus
These instructions use inherent mode. A TSTA or TSTB instruction
automatically subtracts zero from the contents of the subject
accumulator, then sets or resets the N and Z flag accordingly.
These instructions leave the target accumulator unchanged.
Z flag is set if accumulator contains $00.
N flag is set if the 7th bit of the accumulator is set
• BITA – AND the contents of ACCA with the contents of memory byte.
Set or reset the N and Z flags accordingly. ACCA and memory byte
are unaffected.
• BITB -- AND the contents of ACCB with the contents of memory byte.
Set or reset the N and Z flags accordingly. ACCB and memory byte
are unaffected.
• for example to test bit 4 of ACCA BITA #$10 can be used. $10 is
mask byte
• BITA and BITB can access a memory location using immediate, direct,
extended or indexed modes ACCA can be loaded with the mask and
then accessing the memory byte to be tested using immediate, direct,
extended or indexed mode. Suppose the bits 3 and 7 of memory
location $C01Ahas to be tested, then
LDAB #88
BITB C01A
The BITB instruction ands the contents of ACCB and address $C01A
and then updates N and Z accordingly.
• BITA and BITB instructions automatically resets the V flag. The other
flag bits are unchanged.
Using MM and space bar user can enter string of data/program bytes to
consecutive RAM/EEPROM locations.
• Block Fill (BF):
used to load a string of memory address with a constant value.
BF B60A B71D A1
loads addresses $B60A, $B71D and all intervening locationswith the
value $A1.
• MOVE Command:
used to copy the contents of block of addresses to RAM or EEPROM
MOVE 0 2A B700
copies the block of data with addresses from $0000 to $002A to the
block with starting address $B700
• Go (G) Command:
It causes the M68HC11 to execute program,
G B710
Executes the program which is stored at an starting address $b710. in
response to this PC is loaded with 4B710
B3
OPTION Register
• CME bit – 1 enable, 0 disable the clock monitor detect circuitry.
• Any chip reset clears the CME bit, so only program instruction can
enable the clock monitor detect circuitry.
• If internal clocks have completely stopped, the RESET remains low
and will not go back high. In such cases the CPU cannot vector to a
service routine. Then the user has to correct it.
• During the 6th E clock cycle after the RESET pin was driven low, the
M68HC11 checks it again. If it is still low, the M68HC11 assumes that
a POR or external circuit caused the reset. If it returned high before 6
E clock cycles have elapsed, the M68HC11 assumes that the clock
monitor has detected slow clock or that the CPU is lost. In this case
the M68HC11 makes further check to determine whether the clock
monitor caused the reset. If so the CPU vectors to an appropriate
reset response routine.
The computer operating properly (COP) system forms the 4th reset
source. This system detects “hung up” or lost M68HC11 CPU and in
such cases it drives RESET pin low for 4 E clock cycles, then driving
back high.
The COP system uses a timer. This timer operates when the COP is
enabled and the CPU executes program instructions. With the COP
enabled the CPU must write $55 and then $AA to a control register
before the timer times out. If not the COP causes reset. Writing these
causes the timer to begin a new time out.
NOCOP
B2
CONFIG REGISTER
To enable the COP system, the user must reset the NOCOP bit. The
reader cannot program the CPU to write a zero to NOCOP, and
thereby turn on the COP system. Rather, MOVE a control byte from
RAM to CONFIG, using the BUFFALO MOVE command. As long as
NOCOP remains reset, the COP system operates every time the
M68HC11 executes a program. Two bits in the OPTION register give
the system designer a choice of four timeout periods. Motorola calls
these bits the COP timer rate select bits, CR1 and CR0. The four
COP timeouts derive from the M68HC11’s E clock. Internal clock
divider divide the E clock frequency by 215. This E/ 215 frequency
feeds the COP timer. CR1/CR0 bit settings cause the COP timer to
divide the E/ 215 frequency by 1, 4, 16, or 64.
Program Flow
NOCOP = 0
3. Execute application
program instructions
Reset Actions:
M68HC11 takes the following actions when it’s RESET pin is driven
low:
B7 B6 B5 B4 B3 B2 B1 B0
RESET = 0 0 0 0 0 0 0 1
INIT REGISTER
Overall the M68HC11 initializes bits in 24 control registers when its RESET
pin is driven low. These bits establish most of the conditions listed
above.
When the RESET pin rises from low to high the CPU copies the address of
an appropriate reset service routine to its program counter then
executes that routine. These reset routines are loaded at addresses
$E000,$00FA and $00FD. The addresses for different routines are as
follows:
POR/external circuitry --- $E000 (in ROM).
Clock monitor system ---- $00FD (RAM).
COP system ----- $00FA (RAM).
These addresses are copied to the PC from ROM. Three pairs of ROM
locations contain these addresses:
1. $FFFE and $FFFF ----- $E000.
2. $FFFC and $FFFD ----- $00FD.
3. $FFFA and $FFFB ------ $00FA.
in the case of clock monitoring & COP reset the BUFFALO O. S.
uses pseudovectors. Pseudovector is a JMP instruction which re-
vectors the CPU to the ISR’s starting address
INTERRUPTS:
• Types:
• 12 types are there. 7 are special purpose and 5 are general
purpose.
1. Serial Communication Interface uses SCI Serial System interrupt.
Used for a variety of control or error detection purposes.
2. Serial Peripheral Interface (SPI) facilitates synchronous two way
data exchanges between microcontroller and external devices. The
SPI uses SPI Serial Transfer Complete Interrupts to control data
transmission over SPI lines
3. The M68HC11’s pulse accumulator counts the no.of times an
external device applies specified rising and/or falling edges to an
input pin. A Pulse Accumulator Input Edge Interrupt occurs each
time the external device applies a specified edge to the pulse
accumulator’s i/p pin.
4. The Pulse Accumulator maintains its i/p edge count in a special 8 bit
register. Pulse Accumulator Overflow Interrupts can interrupt the
CPU each time the count register’s 8 bit contents roll over from $FF
to $00.
5. The M68HC11 incorporates a flexible and sophisticated timer
section. This timer section bases a wide variety of functions on a 16
bit, free-running counter. The Timer Overflow Interrupt can interrupt
the CPU each time the free-running count rolls over from $FFFF to
$0000.
6. The M68HC11’s timer section includes an Output Compare feature.
Output compare mechanisms compare 16 bit values, established by
the user, with the free-running count, each time this count
increments. When a match occurs, the o/p compare mechanism
drives an assigned o/p pin to a user-specified level.
7. The M68HC11’s timer section also includes Input Capture
mechanisms. Each i/p capture mechanism monitors an assigned
M68HC11 i/p pin. When a peripheral drives this pin with a specified
edge, the i/p capture mechanism records the free-running count.
Each i/p capture mechanism includes an I/p Capture Interrupt.
When enabled, an I/p capture mechanism interrupts the CPU when
it detects a specified edge at its assigned pin.
The above 7 types are special purpose interrupts. The rest are the
general purpose interrupts.
A user cannot disable illegal opcode traps. The user generates s/w
interrupts by writing an SWI instruction into the program. Of the
remaining 10 interrupt types all are maskable at the global level
(CCR), and nine are also masked locally by bits in control registers.
The CCR’s X bit masks XIRQs globaly. Any M68HC11 reset sets X
to 1 and X=1 inhibits XIRQ interrupts. S/w can enable XIRQ
interrupt by resetting X to 0. But s/w cannot change X from 0 to 1.
So once enabled it cannot be disabled except by resetting the
microcontroller. So XIRQs are Pseudo Nonmaskable interrupts. The
TAP instruction can be used to reset X bit.
The M68HC11 masks the following interrupts at both the global and
local levels.
• SCI Serial System Interrupts
• SPI Serial Transfer Complete Interrupts
• Pulse Accumulator Input Edge Interrupts
• Pulse Accumulator Overflow Interrupts
• Timer Overflow Interrupts
• Timer Output Compare Interrupts
• Timer input Capture Interrupts
• Real Time Interrupts (RTI)
• Interrupt requests (IRQ)
The CCR’s I bit (bit 4)enables and disables these interrupts at the
global level. Clearing the I mask enables these interrupts and setting
the I mask disables them.
A user can use the instructions SEI and CLI to set or clear the I
mask
Only the I bit can mask IRQ generated interrupts. IRQs generated
by the parallel I/O mechanisms are masked locally and by global I
mask
• The last instruction in the ISR is RTI. An RTI instruction causes the
CPU to pull its original context from the stack and restore all registers
to their original conditions - at the time the interrupt was generated.
When pulling data from the stack, the M68HC11 increments the SP
by 1 then pulls a byte from the stack.
I Maskable Interrupt Priorities:
• Illegal opcode, SWI and XIRQ have supreme priority since they are
nonmaskable. The user can program the CPU to promote any other
interrupt to highest I maskable interrupt. The promotion routine must
set the I mask, write promotion bits to the HPRIO register, then reset
the I mask to permit interrupts.
B3 B2 B1 B0
PSEL3 PSEL2 PSEL1 PSEL0
The first instruction sets the I mask. The PSEL bits are not writable
unless I = 1, inhibiting I maskable interrupts.
I=1 and
COP SCI Tx disabled?
no no
disabled?
yes yes
Power down timer section Power down SCI Tx
yes
S=1?
no
Stop all internal clocks
Resume fetch and execute
STOP Recovery
yes
DLY=0?
no yes
X=1?
Delay for 4064 E clock
cycles(OSC stabilization)
no
no
DLY – bit 4 in OPTION reg. Enable Oscillator Start Up Delay --- on exit from STOP
• Any reset establishes the DLY bit’s default condition as zero.
Initialize SP
4,7K
19 IRQ Initialize IRQ pseudovector
M68HC11
Clear location $0000
Clear I mask
Call delay
Return
Main ISR
LDS #1FF 0120 INC 0
LDD #120 JSR 130
STD EF RTI
CLR 0
CLI DELAY
010C JSR 130
BRA 10C Load loop counter (ACCA) with $06
5V
4.7K
18 XIRQ
M68HC11
MAIN(WAI) MAIN(STOP)
Initialize SP Initialize SP
C040 INC 0
XIRQ
LDAA #6
C045 LDX #D600
Increment location counter C048 DEX
BNE C048
Execute one second delay
DECA
BNE C045
RTI
Return
Illegal Opcode Interrupts:
NOP A
• The CPU calls the BUFFALO .OUTRHL utility subroutine. This
subroutine converts ACCA’s low nibble (0) to ASCII and writes it to
the terminal display. After displaying 0 the CPU executes another 1
second delay.
• If it encounters an illegal opcode while executing the MAIN program
the CPU vectors to the ILLOP ISR at address $0130. ILLOP causes
the CPU to display on the terminal screen ILLOP @ $XXXX
where $XXXX is the program address of the illegal opcode.
ILLOP
Return
A Software Interrupt Demonstration:
Initialize SP
Compare X reg with address of
Initialize SWI pseudovector ADDOP5+1
yes
Store next operand to ADDOPx Not equal B
(pointed at by X reg.
no
Halt
Increment X and Y reg
SWI
yes
no return
Not equal
PARALLEL I/O
The M68HC11 has the following resources for implementing parallel i/o.
• PORTB data register. It drives output pins PB0-PB7. this is an
output port only.
• PORTC data register. This port can be configured as either input or
output.
• Data Direction Register for PORTC(DDRC). This is used to
configure PORTC pins as input or output bits. Writing a 1 to a DDRC
bit configures the corresponding PORTC pin as an output. Writing a
0, configures as input. With a system reset all DDRC bits reset and
configure all PORTC pins as inputs.
• PORTA and PORTD can also be used for general purpose parallel
I/O
Parallel I/O program flow:
Read PORTC
PC3-PC0
Initialize DDRC to
Configure PC3-PC0 as inputs
And PC7-PC4 as outputs
Store
PORTC read data
Read complete
Write to PORTC:
Initialize DDRC to
Configure PC3-PC0 as inputs
Write PORTC
And PC7-PC4 as outputs
Read PORTC
Load PORTC
Write data
Read PORTC data
to an accumulator.
Write data to PORTC
Address and data buses are connected to PORTB and PORTC pin. Thus
in this mode PORTB and PORTC pins cannot be used for parallel I/O
Four bits in the HPRIO register put the M68HC11 into one of four
hardware modes.
HPRIO High Nibble Bit values Hardware mode
%0000 Single Chip
%0010 Expanded Multiplexed
%1101 Special Bootstrap
%0111 Special Test
Single Chip Mode: In this mode the M68HC11’s s/w resides in on chip
memory. The address and data buses are also internal and unavailable
to external devices,
Expanded Multiplexed Mode: In this mode the M68HC11 connects its
address and data buses , read/write line and an address strobe to
external pins. Expanded mode allows the user to connect external
extended memory for applications requiring large amounts of s/w and
data storage.
Special Bootstrap Mode: In this mode instead of vectoring to a reset
routine, the M68HC11 automatically uploads a 256 byte user program
via its SCI and executes this program. Motorola designates bootstrap
as a special version of single chip mode.
However the M68HC11 CPU can connect its internal buses to external
pins as a part of the uploaded bootstrap program.
Special Test Mode: This mode facilitates production testing of M68Hc11
chips. This mode overrides a number of on chip protective
mechanisms.
HPRIO Register
B7 B0