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Memory Paging
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 INTEL 80386
ARCHITECTURE
A memory management technique in which process address space is broken into
blocks of the same size called pages (size is power of 2, between 512 bytes and
8192 bytes). The size of the process is measured in the number of pages.

Furthermore, main memory is divided into small fixed-sized blocks

of (physical) memory called frames and the size
of a frame is kept the same as that
of a page to have optimum utilization of the main memory
 : Addresses

LINEAR ADDRESS is defined as the address generated by a program.

PHYSICAL ADDRESS is the actual memory location accessed by a program.
With the memory paging unit,

the linear address is invisibly translated to any

physical address
which allows an application
written to function at a specific address
to be relocated through the
paging mechanism.

It also allows memory to be placed into areas where no memory exists

In Windows, each application is allowed a 2G linear
address space from location
00000000H–7FFFFFFFH even though there may not
be enough memory or memory available at
these addresses. Through paging to the hard disk
drive and paging to the memory through the
memory paging unit, any Windows application can
be executed.
Paging unit is controlled by the contents of the
microprocessor’s control registers

Note that these registers are available to the 80386

through the Core2 microprocessors.
PCD specifies whether the cache must be enabled or
disabled while accessing data included in the page frame.
PWT specifies whether write back or write through
strategy(memory
The page directorycaching techniques)
contains 1024must be applied
directory
while writing data into the page frame.
entries of 4 bytes each. Each page directory
entry
If PCD addresses
is set(1), theaPCD
page
pin table that
becomes contains
a logic 1024
one during
bus cycles that are not paged. This allows the external
entries.
hardware to control the level 2 cache memory.The PWT
bit also appears on the PWT pin during bus cycles that
are not paged to control the write-through cache in the
system.
Because the act of repaging a 4K-byte section of memory requires access
to the page directory and a page table, which are both located in memory,
Intel has incorporated a special type of
cache called the TLB (translation look-aside buffer).

In the 80486 microprocessor, the cache holds the 32 most

recent page translation addresses. This means that the last 32 page table
translations are stored in the TLB, so if the same area of memory is accessed,
the address is already
present in the TLB, and access to the page directory and page tables is not
required. This speedsprogram execution. If a translation is not in the TLB, the
page directory and page table must be accessed, which requires additional
execution time.
Page Directory and
Page table
Figure 2-13 shows the page directory a few page tables and some memory pages
●

●There is only one page directory in the system

●The page directory contains 1024 double word addresses that locate up to

1024 page tables

●Page directory and each page table is 4K bytes in length
●DOS systems and EMM386.EXE use page tables to
redefine the area of memory between locations
C8000H-EFFFFH as upper memory blocks
●This is done by re paging extended memory to back

fill this part of the conventional memory system to

allow DOS access to additional memory
Example
Example
Suppose that EMM386.EXE program allows
access to 16M bytes of extended and
conventional memory through paging and
locations C8000H-EFFFFH must be re paged to
locations 110000-138000H with all areas of
memory paged to their normal locations
●The page directory contains four entries(1 entry= 4M bytes of
physical memory)
●The system also has four page tables with 1024 entries each (1

entry=4K bytes of physical memory)

●In total this scheme requires 16K of memory for the four tables

and 16 bytes memory for the page directory

Sources:
https://www.tutorialspoint.com/operating_system/os_memory_mana
gement.htm
https://image.slidesharecdn.com/salientfeatursof80386-
140822084001-phpapp02/95/salient-featurs-of-80386-6-
638.jpg?cb=1408709884
https://en.wikipedia.org/wiki/Control_register
https://books.google.com.ph/books?id=h0lltXyJ8aIC&pg=PT86&lpg=PT
86&dq=PCD+and+PWD+control+register&source=bl&ots=gO8uFT9cK
W&sig=sZECvnEJS0erIvO3yWgXM5wy4aQ&hl=en&sa=X&ved=0ahUKE
wiz-
9bK6urUAhUJKZQKHXnxDHAQ6AEIJjAA#v=onepage&q=PCD%20&f=fals
e