System Design Lab

Introduction
VLSI SYSTEM DESIGN FLOW
FPGA Design Flow
Artix7 Architecture
Configurable Logic Block (CLB)

• 4 six input LUT

• Carry chain
• Multiplexers
• Flip flops
LUT
Constraints
(xdc)
Design Implementation Steps
Synthesis HDL parsing, low level optimization, technology mapping, change to tool specific database

ngc

Translate The Translate process merges all of the input netlists and design constraints and outputs a Xilinx native
generic database (NGD) file, which describes the logical design reduced to Xilinx primitives.

ngd

The Map process maps the logic defined by an NGD file into FPGA elements, such as CLBs and IOBs. The
Map output design is a native circuit description (NCD) file that physically represents the design mapped to the
components in the Xilinx FPGA.
ncd

Place & Route The Place and Route process takes a mapped NCD file, places and routes the design, and produces an
NCD file.

ncd

Generate The Generate Programming File process produces a bit stream for Xilinx device configuration.
bit file

bit
• Constraints File (Location , Timing )
• Ensure that reports and logs are properly analysed
• Before proceeding ensure there are no critical warnings
Timing Verification

• Run static timing analysis at the following points in the design flow:
1. After Map
2. After Place & Route

• Run timing simulation at the following points in the design flow:

1. After Map (for a partial timing analysis of CLB and IOB delays)
2. After Place and Route (for full timing analysis of block and net delays)
Board Interfaces
Open new project
New Verilog file
Select FPGA part
Finished creating project
Decoder logic added in file
Run Synthesis
Synthesis report
Open synthesized design
Device Schematic
Add constraints file
Add required constraints
Schematic after implementation
Schematic
Placement Report
Bit Stream Generation
FPGA Programming
Basys3 Board
Driver Installation
• /home/guest/Vivado/2016.2/data/xicom/cable_drivers/lin64/install_script/install_drivers
Reference Docs
• Vivado – User Guides (ug892)
• FPGA – DataSheet,Library Guide (ds180_7,ug953)
• Board – Schematic , Reference Manual