EDK Overview

© 2004 Xilinx, Inc. All Rights Reserved

 Objectives
After completing this module, you will be able to:
• Describe the embedded systems development flow
• Understand the components in the hardware design
• Specify ways to create a hardware design
• Identify the tools included in the EDK
• Locate the EDK documentation
• List the supported operating systems

EDK Overview - 1 - 3 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Outline
• Introduction
• EDK
– Project Management
– Software Application
Management
– Platform Management
• Hardware Design
• PlatGen
• Supported Platforms

EDK Overview - 1 - 4 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Embedded Systems
• An embedded system is nearly any computing system (other than a
general-purpose computer) with the following characteristics
– Single-functioned
• Typically, is designed to perform predefined function
– Tightly constrained
• Tuned for low cost
• Single-to-fewer components based
• Performs functions fast enough
• Consumes minimum power
– Reactive and real-time
• Must continually monitor the desired environment and react to changes
– Hardware and software co-existence

EDK Overview - 1 - 5 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Embedded Systems
• Examples:
– Mobile phone systems
• Customer handsets and base stations
– Automotive applications
• Braking systems, traction control, airbag release systems, and cruise-control
applications
– Aerospace applications
• Flight-control systems, engine controllers, auto-pilots and passenger in-flight
entertainment systems
– Defense systems
• Radar systems, fighter aircraft flight-control systems, radio systems, and
missile guidance systems

EDK Overview - 1 - 6 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Current Technologies
• Microcontroller-based systems
• DSP processor-based systems
• ASIC technology
• FPGA technology

EDK Overview - 1 - 7 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Integration in System Design
Embedded Software Tools

CPU Logic + Memory

Integration of Functions

+ IP +
CPU Embedded Software Tools Processors +
RocketIO
Embedded Software Tools
(Virtex-II Pro)
FPGA + Logic Design Tools
FPGA Memory + IP +
High Speed IO
(4K & Virtex)
Programmable Systems
I/O usher in a new era of system
Logic Design Tools
design integration
possibilities
Memory

Logic Design Tools

Time
EDK Overview - 1 - 8 © 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
 Embedded Design
in an FPGA
• Embedded design in an FPGA consists of the following:
– FPGA hardware design
– C drivers for hardware
– Software design
• RTOS versus Main + ISR

EDK Overview - 1 - 9 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 PowerPC-based Embedded Design
RocketIO
Dedicated Hard IP
DSOCM ISOCM
BRAM PowerPC BRAM Flexible Soft IP
405 Core IBM CoreConnect™
DCR Bus on-chip bus standard
Instruction Data
PLB, OPB, and DCR

PLB OPB
Arbiter

Arbiter
Bus
Processor Local Bus On-Chip Peripheral Bus
Bridge

e.g.
Hi-Speed Memory GB On-Chip
UART GPIO
Peripheral Controller E-Net Peripheral

Off-Chip ZBT SSRAM Full system customization to meet

Memory DDR SDRAM performance, functionality, and
SDRAM cost goals

EDK Overview - 1 - 10 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 MicroBlaze-based Embedded Design

I-Cache
Local Memory BRAM Flexible Soft IP
BRAM MicroBlaze
Configurable
Bus 32-Bit RISC Core Sizes
D-Cache Possible in Dedicated Hard IP
BRAM Virtex-II Pro PowerPC
405 Core
Instruction Data
LocalLink™ OPB
Arbiter

Arbiter
FIFO Channels PLB
Bus
On-Chip Peripheral Bus Bridge
Processor Local Bus
0,1…….32
e.g.
Hi-Speed Memory GB
Custom Custom Peripheral Controller E-Net

Functions Functions
10/100 On-Chip
UART
E-Net Peripheral

Off-Chip FLASH/SRAM
Memory

EDK Overview - 1 - 11 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Outline
• Introduction
• EDK
– Project Management
– Software Application
Management
– Platform Management
• Hardware Design
• PlatGen
• Supported Platforms

EDK Overview - 1 - 12 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Embedded Development
Tool Flow Overview
Standard Embedded SW Standard FPGA HW
Development Flow Development Flow
C Code VHDL/Verilog

Compiler/Linker Synthesizer
(Simulator) Simulator

Object Code Place & Route

Data2MEM
? ?
CPU code in CPU code in
Bitstream
off-chip on-chip
memory memory Download to FPGA

Download to Board & FPGA

Debugger

EDK Overview - 1 - 13 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 EDK
• The Embedded Development Kit (EDK) consists of the following:
– Xilinx Platform Studio – XPS
– Base System Builder – BSB
– Creating/Importing IP Wizard
– Hardware generation tool – PlatGen
– Library generation tool – LibGen
– Simulation generation tool – SimGen
– GNU software development tools
– System verification tool – XMD
– Processor IP
– Drivers for IP
– Documentation
• Use the GUI or the shell command tool to run the EDK tool

EDK Overview - 1 - 14 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 EDK
MHS File Source Code
Source Code
system.mhs

MSS File
Processor IP PlatGen Synthesis Compile system.mss
MPD Files

EDIF Object Files LibGen

IP Netlists

system.ucf ISE/Xflow Link Libraries

system.bit Data2MEM Executable

download.bit

Hardware

EDK Overview - 1 - 15 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Xilinx Platform Studio

System Source
Diagram Code
View Editor
System
Details
View

Integrated Hardware and Software

System Development Tools

EDK Overview - 1 - 16 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 XPS Functions
• Project management • Platform management
– MHS or MSS file – Tool flow settings
– XMP file – Software platform settings
• Software application – Tool invocation
management – Debug and simulation

Hardware HW/SW
Design Simulation

XPS
Software HW/SW
Design Debug

EDK Overview - 1 - 17 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Outline
• Introduction
• EDK
– Project Management
– Software Application
Management
– Platform Management
• Hardware Design
• PlatGen
• Supported Platforms

EDK Overview - 1 - 18 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Project Management
• Create a new project
– Using Base System Builder
– Using Platform Studio
– New Project toolbar button
• Opens a Platform Studio GUI
• Open an existing project
– Import existing MHS file
– Select the Target Device
– Specify a single Peripheral Repository
• Project information is saved in the Xilinx Microprocessor Project
(XMP) file

EDK Overview - 1 - 19 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Create a Project Using Base
System Builder (BSB)
• Select a target board
• Select a processor
• Configure the processor
• Select and configure
I/O interfaces
• Add internal peripherals
• Generate the system software
and the linker script
• Generate the design
– system.mhs
– data/system.ucf
– etc/fast_runtime.opt
– etc/download.cmd
– system.bsb (optional, if selected)
– TestApp/src/TestApp.c (optional, if selected)
– TestApp/src/TestAppLinkScr (optional, if selected)

EDK Overview - 1 - 20 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Project Creation Using BSB
1
Identify Location and
Project File Name

2
Select a Board Vendor,
Name, and Revision

2AAlternatively, you can start

with an already built
project and make changes

EDK Overview - 1 - 21 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Project Creation Using BSB

4 Configure the processor and

3 bus speeds, and debug
Select a processor

EDK Overview - 1 - 22 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Project Creation Using BSB
5
Select and configure I/O

6
Add internal peripherals

Number of peripherals
5A displayed will depend on the
screen size and resolution

EDK Overview - 1 - 23 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Project Creation Using BSB
7 Configure software
application and linker script

7A Assign stdin and stout

devices if present

7B Assign memory blocks

Deselecting this option for various purposes
7C
will not generate software
application and linker script

EDK Overview - 1 - 24 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Project Creation Using BSB

8
Generate the system

EDK Overview - 1 - 25 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Project Creation
Through Platform Studio

or

1
Identify Location and
Project File Name

2
Identify Target Device

EDK Overview - 1 - 26 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Project Creation
Through Platform Studio
Select and Edit the Address
Map for Each Module
4

3 Select modules from the

catalog and click Add to
instantiate them in your
design

EDK Overview - 1 - 27 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Project Creation
Through Platform Studio

Add buses to the project

5

Identify the bus to which

modules are attached as Slave
or Master
6

EDK Overview - 1 - 28 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Outline
• Introduction
• EDK
– Project Management
– Software Application
Management
– Platform Management
• Hardware Design
• PlatGen
• Supported Platforms

EDK Overview - 1 - 29 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Software Application
Management
• XPS supports test application creation and linker script management
through BSB
• XPS allows users to specify multiple application projects in the
Applications tab
• XPS has an integrated editor for viewing and editing the C source and
header files of the user program
• The source code is grouped for each processor instance. You can add
or delete the list of source code files for each processor
• All of the source code files for a processor are compiled by using the
compiler specified for that processor
• XPS tracks changes to C/C++ source files and recompiles when
necessary

EDK Overview - 1 - 30 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Outline
• Introduction
• EDK
– Project Management
– Software Application
Management
– Platform Management
• Hardware Design
• PlatGen
• Supported Platforms

EDK Overview - 1 - 31 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Process Management
• Platform management tasks of XPS include
– Librarie and device driver configuration (LibGen)
– Simulation model generation (SimGen)
– Implementation (Xflow or ISE)
– Compilation (GNU Compiler)
– Bitstream initialization (Data2MEM)
• To change the system specification and software settings, XPS supports
the following features and processes
– Add/Edit Cores (Dialog)
– Software Platform Settings
– Tool Flow Settings
– Tool Invocation

EDK Overview - 1 - 32 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Add/Edit Cores (Dialog)
• Design and modify the hardware system
– Add peripherals
• Processor: PowerPC or MicroBlaze
• Bus: PLB, OPB, OCM
• Add bus-specific IP
• Customize IP
– Delete peripherals
• Processor
• Bus-specific IP
• Custom IP
– Change (add/delete/modify) settings
• Base address and end address
• Parameters
• Ports

EDK Overview - 1 - 33 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Software Platform Settings
• Used to set all the software platform related options in the design
• Has multiple tabs
– Software Platform
• Drivers
• Libraries
• Kernel and Operating Systems
– Processor and Drivers Parameters
• Compilers
• Core clock frequency
– Library/OS Parameters
• Stdin and stdout devices
• Malloc function usage option

EDK Overview - 1 - 34 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Project Options Settings
• XPS supports project options settings for
– Device and Repository
– Hierarchy and Flow
– Simulation

EDK Overview - 1 - 35 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Project Options
Device and Repository Tab
• Set/Change Target Device
– Architecture
– Device Size
– Package
– Grade
• Peripheral Repository Directory
– Provide path to custom IP
not present in the current
project directory structure
• Custom Makefile Directory

Note: Detailed information on the other

two tabs is provided in the Adding
Your Own IP to the OPB Bus module and the System Simulation module

EDK Overview - 1 - 36 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Outline
• Introduction
• EDK
– Project Management
– Software Application
Management
– Platform Management
• Hardware Design
• PlatGen
• Supported Platforms

EDK Overview - 1 - 37 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Hardware Design Example
• We will build the following system from scratch
(while no components are present in the system)
OPB
PLB Bus
Bus
UART

INTC
PLB2OPB
PPC
PLB BRAM Timer
Cntlr PLB BRAM

PLB BRAM GPIO

Cntlr PLB BRAM
GPIO
MY IP
• We will start with GPIO
Project  Add/Edit Cores … (Dialog)

EDK Overview - 1 - 38 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Add/Edit Cores
Peripherals Tab
• In XPS, select
Project  Add/Edit
Cores... to open
the System Settings
dialog
• Select one or more
cores to be included
into the system MHS
file, then click << Add

EDK Overview - 1 - 39 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Embedded Design Progress
OPB
Bus
PLB
Bus UART

INTC
PLB2OPB
PPC
Timer
PLB BRAM
Cntlr PLB BRAM
GPIO
PLB BRAM
Cntlr PLB BRAM
GPIO
MY IP
GPIO

Having placed the processor and peripherals, add buses

EDK Overview - 1 - 40 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Add/Edit Cores
Bus Connections Tab
1• Select and add the
buses required in the 1
system
2
2• Specify the bus
to which each peripheral
is connected as master
or slave 3
3• Specify the BRAMs
to the correct
Memory Controllers

EDK Overview - 1 - 41 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Hardware Design Progress
OPB
Bus
PLB
Bus UART

INTC
PLB2OPB
PPC
Timer
PLB BRAM
Cntlr PLB BRAM
GPIO
PLB BRAM
Cntlr PLB BRAM
GPIO
MY IP
GPIO

Having assigned bus connections, connect internal and external ports

EDK Overview - 1 - 42 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Add/Edit Cores
Ports Tab
1• Filter ports by 1
instance or string 3 4 5
2• Add/Remove
ports to be
connected
3• Connect 2
component ports
using nets and
Specify net names
4• Specify if a net is
internal or external
5• Specify net sizes

EDK Overview - 1 - 43 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Defining a Connection
1 Select ports to be
connected (use Shift 1
or Ctrl keys)

2 Click Connect

3 Enter the net name used

for the connection
3 2

4 Specify whether a net is 4

internal or external

EDK Overview - 1 - 44 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Hardware Design Progress
PowerPC Processor System Reset
RSTC405RESETCHIP RSTC405RESETCHIP
RSTC405RESETCORE RSTC405RESETCORE
RSTC405RESETSYS RSTC405RESETSYS
C405RSTCHIPRESETREQ CHIP_RESET_REQ
C405RSTCORERESETREQ CORE_RESET_REQ
C405RSTSYSRESETREQ SYSTEM_RESET_REQ

JTAG PPC
JTGC405TCK JTGC405TCK
JTGC405TDI JTGC405TDI
JTGC405TMS JTGC405TMS
JTGC405TDO JTGC405TDO
JTGC405TDOEN JTGC405TDOEN

Once ports are connected, each device can be configured

for specific functionalities

EDK Overview - 1 - 45 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Add/Edit Cores
Parameters Tab
1 Define the IP Peripheral
parameters for each
core
3
2 Default values are Overriding 2
shown values
1
3 Overriding values Default values
can be entered

EDK Overview - 1 - 46 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Outline
• Introduction
• EDK
– Project Management
– Software Application
Management
– Platform Management
• Hardware Design
• PlatGen
• Supported Platforms

EDK Overview - 1 - 47 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 EDK
MHS File
system.mhs Source Code Source Code

MSS File
Processor IP Synthesis Compile system.mss
PlatGen
MPD Files
EDIF LibGen
Object Files
IP Netlists
Focus Here
system.ucf ISE/Xflow Link Libraries

system.bit Data2MEM Executable

download.bit

Hardware

EDK Overview - 1 - 48 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Hardware Design
• Platform Generator (PlatGen) inputs the following files:
– MHS file
– MPD file
• PlatGen constructs the embedded processor system in the form of
hardware netlists (HDL and implementation netlist files)
• MHS file parameters override the MPD parameters
– The MPD parameters are the defaults

EDK Overview - 1 - 49 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Hardware Design
Microprocessor Hardware
Specification File

Microprocessor Peripheral
Definitions File

MHS overrides MPD

MPD contains all of the defaults
EDK Overview - 1 - 50 © 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
 PlatGen
PlatGen Generated Directories
project_directory
hdl directory
implementation directory
synthesis directory
EDK Overview - 1 - 51 © 2004 Xilinx, Inc. All Rights Reserved
• HDL directory
– system.[vhd|v] file (if top-level)
– system_stub.[vhd|v] file (if sub-module)
– peripheral_wrapper.[vhd|v] files
• Implementation directory
– peripheral_wrapper.ngc files
– system.ngc file
– system.bmm file
• Synthesis directory
– peripheral_wrapper.[prj|scr] files
– system.[prj|scr] files
For Academic Use Only
 PlatGen Memory Generation
• Memory generation
– Platform Generator generates the necessary banks of memory and the
initialization files for the BRAM block (bram_block). The BRAM block is
coupled with a BRAM controller
– Current BRAM controllers include the following:
• DSOCM BRAM Controller (dsbram_if_cntlr)
• ISOCM BRAM Controller (isbram_if_cntlr)
• PLB BRAM Controller (plb_bram_if_cntlr)
• OPB BRAM Controller (opb_bram_if_cntlr)
• LMB BRAM Controller (lmb_bram_if_cntlr)

EDK Overview - 1 - 52 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 PlatGen Memory Sizes
• Memory sizes

OPB, LMB, OCM Buses PLB Bus

• Memory must be built on 2n boundaries

– Let n be the number of address pins on the memory, and let I be the unsigned
number formed by the starting address or memory size. If I is the integer, then the
memory is built on the 2n boundary
– One-KB memory at $4000 is at the 2n boundary; whereas, one KB at $4100 is not
EDK Overview - 1 - 53 © 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
 BlockMemory Map
• A BMM (BlockRAM Memory Map) file contains a syntactic description of
how individual BlockRAMs constitute a contiguous logical data space
• PlatGen has the following policy for writing a BMM file:
– If PORTA is connected and PORTB is not connected, then the BMM
generated will be from PORTA point of reference
– If PORTA is not connected and PORTB is connected, then the BMM
generated will be from PORTB point of reference
– If PORTA is connected and PORTB is connected, then the BMM generated
will be from PORTA point of reference

EDK Overview - 1 - 54 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Outline
• Introduction
• EDK
– Project Management
– Software Application
Management
– Platform Management
• Hardware Design
• PlatGen
• Supported Platforms

EDK Overview - 1 - 55 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Supported Platforms
• Operating systems
– Windows 2000 (Service Pack 2)
– Windows XP
– Solaris 2.8/2.9
– Linux Red Hat
• FPGA families
– Spartan-II (MicroBlaze)
– Spartan-IIE (MicroBlaze)
– Spartan III (MicroBlaze)
– Virtex  and Virtex E (MicroBlaze)
– Virtex-II (MicroBlaze)
– Virtex-II Pro (MicroBlaze and PowerPC)

EDK Overview - 1 - 56 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 BSB Supported Platforms
• Some of the Hardware boards
– Avnet Virtex-II Pro Development Board
– Avnet Spartan -III Evaluation Board
– Memec design Spartan -IIE Development Boards
– Memec design Virtex-II MicroBlaze Development Board
– Memec design Virtex-II Pro Development Boards
– Xilinx Spartan -III Starter Board
– Xilinx ML300 board
– Xilinx ML310 board
• Others available from the Board Vendor

EDK Overview - 1 - 57 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Review Questions
• What is the smallest memory size that PlatGen can generate for a
Spartan-IIE device?

• Why is the address 0xFFFF_B100, NOT a valid BASEADDR for a LMB

BRAM controller?

• What will the BAUDRATE for the peripheral be:

– If the MPD has the following parameter: C_BAUDRATE = 9600
– If the MHS has the following parameter: C_BAUDRATE = 115200

EDK Overview - 1 - 59 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Answers
• What is the smallest memory size that PlatGen can generate for a
Spartan-IIE device?
– 2 KB
• Why is the address 0xFFFF_B100, NOT a valid BASEADDR for a LMB
BRAM Controller?
– It is not on a 2n boundary
• What will the BAUDRATE for the peripheral be:
– If the MPD has the following parameter: C_BAUDRATE = 9600
– If the MHS has the following parameter: C_BAUDRATE = 115200

EDK Overview - 1 - 60 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Memory Space
• How do you build a 48-KB OPB BRAM memory space for a
MicroBlaze processor in a Virtex-II device?

0x0000_0000

? KB

0x
0x
? KB
0x

EDK Overview - 1 - 61 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Memory Space
• How do you build a 48-KB OPB BRAM memory space for a
MicroBlaze processor in a Virtex-II device?

0x0000_0000

32 KB

0x0000_7FFF
0x0000_8000
16 KB
0x0000_BFFF

EDK Overview - 1 - 62 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Memory Requirement
• How many block RAMs do you think will be used to build a 16-KB PLB
memory space for a PowerPC processor in a Virtex-II Pro device?
And why?

EDK Overview - 1 - 63 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Memory Requirement
• How many block RAMs do you think will be used to build a 16-KB PLB
memory space for a PowerPC processor in a Virtex-II Pro device?
And why?
– Eight block RAMs will be used
– Because PowerPC allows a byte write, the memory is organized in a byte-
wide mode. The Virtex-II Pro block RAM has 18 Kb; each block will be
configured in 2K x 8. This will require eight block RAMs

EDK Overview - 1 - 64 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only
 Where Can I Learn More?
• Tool documentation
– Getting Started with the Embedded Development Kit
– Processor IP Reference Guide
– Embedded Systems Tools Guide
– Xilinx Drivers
• Processor documentation
– PowerPC Processor Reference Guide
– PowerPC 405 Processor Block Reference Guide
– MicroBlaze Processor Reference Guide
• Support website
– Tech Tips: www.support.xilinx.com/xlnx/xil_tt_home.jsp
– EDK Home Page: support.xilinx.com/edk

EDK Overview - 1 - 65 © 2004 Xilinx, Inc. All Rights Reserved

For Academic Use Only