ATPG OVERVIEW C

By ashokraj yellamraju
 Atpg overview
• Atpg means name in the sense automatic test pattern generation, it is generating the
patterns to detect faults.

• sets of 1s and 0s placed on primary input pins during the manufacturing test process to
determine if the chip is functioning properly.

• When the test pattern is applied, the Automatic Test Equipment (ATE) determines if the
circuit is free from manufacturing defects by comparing the fault-free output.
 The ATPG Process
• The goal of ATPG is to create a set of patterns that achieves a given test coverage, where
test coverage is the total percentage of testable faults the pattern set actually detects.

• ATPG consists of two main steps:

• 1) generating patterns

• 2) performing fault simulation to determine which faults the patterns detect.

 methods for pattern generation
• 1) Random Pattern Test Generation : An ATPG tool uses random pattern test generation when it
produces a number of random patterns and identifies only those patterns that detect faults.

• It then stores only those patterns in the test pattern set.

• The type of fault simulation used in random pattern test generation cannot replace
deterministic test generation because it can never identify redundant faults.

• 2) Deterministic Pattern Test Generation : An ATPG tool uses deterministic test pattern
generation when it creates a test pattern intended to detect a given fault.

• The procedure is to pick a fault from the fault list, create a pattern to detect the fault, fault
simulate the pattern, and check to make sure the pattern detects the fault.
Test types
 Fault classes
• 1. Untestable (UT) :
• 1. Unused(UU)
• 2. Tied(TI)

• 3. Blocked(BL)

• 4. Redundant(RE)

• 2. Testable (TE) :
• 1. Detected (DT)

• 2. Posdet (PD)
• 3. ATPG_untestable (AU)
• 4. Undetected (UD)
 1. Untestable (UT) :

1. Unused(UU):

• The unused fault class includes all faults on

circuitry unconnected to any circuit
observation point and faults on floating
primary outputs
2. Tied(TI): • Because tied values propagate, the tied

• The tied fault class includes faults on gates circuitry at A causes tied faults at A, B, C,
and D.
where the point of the fault is tied to a value
identical to the fault stuck value. These are
possible causes of tied circuitry:

Tied signals

AND and OR gates with complementary

inputs

Exclusive-OR gates with common inputs

3. Blocked(BL): equivalent faults.

• The blocked fault class includes faults on

circuitry for which tied logic blocks all paths
to an observable point.

• Note: Tied faults and blocked faults can be

4. Redundant(RE): C. If D is stuck at 1, this fault is undetectable
because the value of G can never change,
• The redundant fault class includes faults the
regardless of the value at D.
test generator considers undetectable.

• After the test pattern generator exhausts all

patterns, it performs a special analysis to
verify that the fault is undetectable under
any conditions.

• In this circuit, signal G always has the value

of 1, no matter what the values of A, B, and
 2. Testable (TE) :
1. Detected (DT):

• The detected fault class includes all faults that the ATPG process identifies as detected.

• The detected fault class contains two groups:

• det_simulation (DS) - faults detected when the tool performs fault simulation(with patterns,
its done during functioning/capture mode)

• det_implication (DI) - faults detected when the tool performs learning analysis(without
patterns, its done during scan paths SI to SO)
2. Posdet (PD):

• The posdet, or possible-detected fault class includes all faults that fault simulation identifies as
possible-detected but not hard detected.

• A possible-detected fault results from a good-machine simulation observing 0 or 1 and the

faulty machine observing X.

posdet_testable (PT) - potentially detectable posdet faults. PT faults result when the tool cannot
prove the 0/X or 1/X difference is the only possible outcome.

• A higher abort limit may reduce the number of these faults.

posdet_untestable (PU) - proven ATPG_untestable during pattern generation and hard

undetectable posdet faults.

• Typically, faults may be classified as PU during ATPG or when the “compress_patterns -reset_au”
command is used.
3. ATPG_untestable (AU):

• The ATPG_untestable fault class includes all faults for which the test generator is unable to
find a pattern to create a test, and yet cannot prove the fault redundant.

• Testable faults become ATPG_untestable faults because of constraints, or limitations,

placed on the ATPG tool (such as a pin constraint or an insufficient sequential depth).

• These faults may be possible-detectable, or detectable, if you remove some constraint, or

change some limitation, on the test generator (such as removing a pin constraint or
changing the sequential depth).

• You cannot detect them by increasing the test generator abort limit.

• The tools place faults in the AU category based on the type of deterministic test generation
method used.
4. Undetected (UD):

• The undetected fault class includes undetected faults that cannot be proven untestable or
ATPG_untestable. The undetected class contains groups:

uncontrolled (UC) - undetected faults, which during pattern simulation, never achieve the
value at the point of the fault required for fault detection—that is, they are uncontrollable.

unobserved (UO) - faults whose effects do not propagate to an observable point.

• All testable faults prior to ATPG are put in the UC category.

• Faults that remain UC or UO after ATPG are aborted, which means that a higher abort limit
may reduce the number of UC or UO faults.

Note: Uncontrolled and unobserved faults can be equivalent faults. If a fault is both
uncontrolled and unobserved, it is categorized as UC.
Fault Class Hierarchy
 Testability Calculations
Test Coverage:

• Test coverage, which is a measure of test quality, is the percentage of faults detected from
among all testable faults.

• Typically, this is the number of most concern when you consider the testability of your design.

• The tool calculates test coverage using the formula:

#DT + (#PD * posdet_credit)

————————————————————x 100
#testable

• In this formula, posdet_credit is the user-selectable detection credit (the default is 50%) given to
possible detected faults with the set_possible_credit command.
Fault Coverage

• Fault coverage consists of the percentage of faults detected from among all faults that the test
pattern set tests—treating untestable faults the same as undetected faults.

• The tool calculates fault coverage using the formula:

#DT + (#PD * posdet_credit)

—————————————————————— x 100

#full
ATPG Effectiveness:

• ATPG effectiveness measures the ATPG tool’s ability to either create a test for a fault, or prove
that a test cannot be created for the fault under the restrictions placed on the tool.

• The tool calculates ATPG effectiveness using the formula:

#DT + #UT + #AU + #PU +(#PT *posdet_credit)

———————————————————————————x 100

#full
 STUCK-AT FAULTS
Single Stuck-at Fault

• Three properties define a single stuck-at fault

1. Only one line is faulty

2. The faulty line is permanently set to 0 or 1

3. The fault can be at an input or output of a gate

• Example: NAND gate has 3 fault sites ( ) and 6 single stuck-at faults
 Fault Equivalence

Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect
f2.

• If faults f1 and f2 are equivalent then the corresponding faulty functions are identical.

Fault collapsing: All single faults of a logic circuit can be divided into disjoint equivalence
subsets, where all faults in a subset are mutually equivalent.

• A collapsed fault set contains one fault from each equivalence subset.
EQUIVALENCE RULES
EQUIVALENCE COLLAPSING EXAMPLE

Faults in orange
color are by
equivalence
collapsing
EQUIVALENCE COLLAPSING ANOTHER EXAMPLE

orange
Fault Dominance:

• If all tests of some fault F1 detect another fault F2, then F2 is said to dominate F1.

Dominance fault collapsing: If fault F2 dominates F1, then F2 is removed from the fault list.
EQUIVALENCE DOMINANCE EXAMPLE
EQUIVALENCE DOMINANCE ANOTHER EXAMPLE
 Select fault types/models during LABS
• set fault type Stuck (default)Fault model to be used for ATPG
• Also: Iddq, Toggle, Transition, Path_delay, Bridge

• Optionally specify “multiple detection” # to require multiple detections of each fault

• add faults –all add faults to current fault list, discarding all patterns and setting all faults to undetected
• options for each fault model; Ex. stuck_at 01 (or 1 or 0)

• set fault mode uncollapsed -include EQ faults

• set fault mode collapsed (don’t report EQ faults)

• write faults <filename>–write fault list to file

• report faults –print list of modeled faults

 IDDQ Test
• IDDQ testing measures quiescent power supply current rather than pin voltage, detecting
device failures not easily detected by functional testing—such as CMOS transistor stuck-on
faults or adjacent bridging faults.

• IDDQ testing equipment applies a set of patterns to the design, lets the current settle, then
measures for excessive current draw. Devices that draw excessive current may have
internal manufacturing defects.

• Because IDDQ tests do not have to propagate values to output pins, the set of test vectors
for detecting and measuring a high percentage of faults may be very compact.

• The ATPG tool efficiently creates this compact test vector set.
Stuck at example
With short
Due to short at
pmos, it results for
high input also it
1 consumes power
AT SPEED TESTING and the Transition Fault Model
• Transition faults model large delay defects • There are 2 methods used to find transition
at gate terminals in the circuit under test. delays

• The transition fault model behaves as a 1. LOS(launch on shift):

stuck-at fault for a temporary period of time. 2. LOC(launch on capture)
• The slow-to-rise transition fault models a
device pin that is defective because its
value is slow to change from a 0 to a 1.

• The slow-to-fall transition fault models a

device pin that is defective because its
value is slow to change from a 1 to a 0.
 LOS
The patterns typically include two cycles. capture cycle, which is usually much faster than the
• During the first capture cycle, the design is kept in shift cycles.
shift mode.
• During the second cycle, the scan enable is de-
asserted and the capture is performed.
• This method is more commonly used because it
allows the tool to perform shift and capture at-
speed using PLL clocks.
• You use a named capture procedure to force
scan_en to change from 1 to 0 at the second
capture cycle.
• The scan_en is typically a pipelined signal, not a PI.
• so it can have at-speed timing to switch at the
 LOC
• This is a clock sequential pattern,
commonly referred to as a broadside
pattern.
• Typically, this type of pattern eases
restrictions on scan enable timing
because of the relatively large amount
of time between the last shift and the
launch.
• After the last shift, the clock is pulsed
at speed for the launch and capture
cycles.
DIFFERENCE BETWEEN LOS AND LOC
 ATPG Tool Pattern Types
• The ATPG tool has several different types of testing modes. That is, it can generate several
different types of patterns depending on the style and circuitry of the design and the
information you specify. By default, the tool generates basic scan patterns.
• Basic Scan Patterns
• Clock PO Patterns
• Clock Sequential Patterns
• Multiple Load Patterns
• RAM Sequential Patterns
• Sequential Transparent Patterns
 Good/Fault Simulation with Existing Patterns

• The purpose of fault simulation is to determine the fault coverage of the current pattern
source for the faults in the active fault list. The purpose of “good” simulation is to verify the
simulation model.

• Typically, you use the good and fault simulation capabilities of the ATPG tool to grade
existing hand- or ATPG-generated pattern sets.