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CMOS VLSI
Design
1
Introduction
Integrated Circuits:
many transistors on one chip
Very Large Scale Integration (VLSI):
very many transistors on one chip
Complementary Metal Oxide Semiconductor (CMOS):
fast, cheap, low power
2
Outline
A Brief History
MOS transistors
CMOS Logic
CMOS Fabrication and Layout
Chip Design Challenges
System Design
Logic Design
Physical Design
Design Verification
Fabrication, Packaging and Testing
3
A Brief History
T-R-A-N-S-I-S-T-O-R = TRANsfer resiSTOR
5
Moore’s Law
In 1963 Gordon Moore predicted that as a result of continuous miniaturization
transistor count would double every 18 months
53% compound annual growth rate over 45 years
No other technology has grown so fast so long
Transistors become smaller, faster, consume less power, and are
cheaper to manufacture
6
Clock Frequencies of Intel Processors
Transistor count is not the only factor that has grown exponentially, e.g.
clock frequencies have doubled roughly every 34 months
7
Integrated Circuits (IC)
8
Chip Integration Level
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The Productivity Gap
Designers rely increasingly on design automation software tools:
• to seek productivity gains
• to cope with increased complexity
Source: SEMATECH 11
Silicon Lattice
Silicon is a semiconductor
Transistors are built on a silicon substrate
Silicon is a Group IV material
Forms crystal lattice with bonds to four neighbors
12
Dopants
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type)
Group III: missing electron, called hole (p-type)
Si Si Si Si Si Si
- +
+ -
Si As Si Si B Si
Si Si Si Si Si Si
13
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large
currents between emitter and collector
Base currents limit integration density
15
nMOS Operation
Body is commonly tied to ground (0 V)
When the gate is at a low voltage:
P-type body is at low voltage
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF
0
n+ n+
S D
p bulk Si
16
nMOS Operation Cont.
When the gate is at a high voltage:
Positive charge on gate of MOS capacitor
Negative charge attracted to body
channel under gate gets “inverted” to n-type
Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
1
n+ n+
S D
p bulk Si
17
pMOS Transistor
Similar, but doping and voltages reversed
Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
p+ p+
n bulk Si
18
Power Supply Voltage
GND = 0 V
In 1980’s, VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny
transistors
Lower VDD saves power
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
19
MOS Transistors as switches
We can model MOS transistors as controlled switches
Voltage at gate controls path from source to drain
20
Types of digital circuits
Combinational
Sequential
21
Logic values and noise
margins
22
CMOS Technology
23
CMOS Logic Inverter
A Y
0 1
1 0
ON OFF
1= 0= =1 =0
OFF ON
24
CMOS Logic NAND
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CMOS Logic NOR
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CMOS Logic Gates (a.k.a. Static CMOS)
27
Compound Gates
Example: Y = (A+B+C) D
ABCD Y
---0 1
0001 1
1--1 0
-1-1 0
--11 0
28
Compound Gates
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How good is the output signal ?
Signal Strength
Strength of signal
How close it approximates ideal voltage source
VDD and GND rails are strongest 1 and 0 sources
nMOS and pMOS are not ideal switches
nMOS pass strong 0, but degraded or weak 1
pMOS pass strong 1, but degraded or weak 0
Thus:
nMOS are best for pull-down network
pMOS are best for pull-up network
30
Pass Transistors
Transistors can be used as switches
31
Transmission Gates
Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well
32
Static CMOS gates are fully restored
33
Static CMOS is inherently inverting
CMOS single stage gates must be inverting
To build non inverting functions we need
multiple stages
34
Tristates
EN A Y
0 0 Z
0 1 Z
1 0 0
1 1 1
35
Nonrestoring Tristates
37
Multiplexers
S D1 D0 Y
S
0 X 0 0
0 X 1 1 D0 0
Y
1 0 X 0 D1 1
1 1 X 1
38
Gate-Level Mux Design
Y = S D0 + S D1
How many transistors are needed? = 20 =
= Too Many !!
D1
S Y
D0
D1 4 2
S 4 2 Y
D0 4 2
2 39
Transmission Gate Mux
Nonrestoring mux uses two transmission gates
Only 4 transistors
40
Inverting Mux
Inverting multiplexer
Use compound gate (a) or pair of tristate inverters (b)
Essentially the same thing
For noninverting multiplexer add an inverter
41
D Latch
When CLK = 1, latch is transparent
D flows through to Q like a buffer
CLK CLK
Latch
D
D Q
Q
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D Latch Design
Multiplexer chooses D or hold Q
CLK
CLK
D Q Q
1
Q D Q
0
CLK CLK
CLK
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D Latch Operation
Q Q
D Q D Q
CLK = 1 CLK = 0
CLK
44
D Flip-flop
When CLK rises, D is copied to Q
At all other times, Q holds its value
a.k.a. positive edge-triggered flip-flop, master-
slave flip-flop
CLK
CLK
D
Flop
D Q
Q
45
D Flip-flop Design
CLK CLK
CLK QM
D Q
CLK CLK CLK CLK
CLK
Latch
Latch
QM
D Q
CLK CLK
46
D Flip-flop Operation
QM Q
D
CLK = 0
QM
D Q
CLK = 1
CLK
47
Summary
48