Why do we need to learn

Microprocessors/controllers?

• The microprocessor is the core of

computer systems.
• Nowadays many communication, digital
entertainment, portable devices, are
controlled by them.
• A designer should know what types of
components he needs, ways to reduce
production costs and product reliable.
 Different aspects of a
microprocessor/controller
• Hardware :Interface to the real world

• Software :order how to deal with inputs

 The necessary tools for a
microprocessor/controller

• CPU: Central Processing Unit

• I/O: Input /Output
• Bus: Address bus & Data bus
• Memory: RAM & ROM
• Timer
• Interrupt
• Serial Port
• Parallel Port
 Microprocessors:
General-purpose microprocessor
• CPU for Computers
• No RAM, ROM, I/O on CPU chip itself
• Example：Intel’s x86, Motorola’s 680x0

Many chips on mother’s board

Data Bus
CPU
General-
Serial
Purpose RAM ROM I/O Timer COM
Micro- Port
Port
processor
Address Bus

General-Purpose Microprocessor System

 What is a microcontroller?

•Microcontroller is a programmable digital

processor with necessary peripherals. Both
microcontrollers and microprocessors are
complex sequential digital circuits meant to
carry out job according to the program /
instructions.
A microcontroller can be compared to a Swiss
knife with multiple functions incorporated in
the same IC.
A Microcontroller compared with a Swiss
knife
 Development/Classification of
microcontrollers
Intel 4004 4 bit (2300 PMOS trans, 108 kHz) 1971

Intel 8048 8 bit 1976

Intel 8031 8 bit (ROM-less) .

Intel 8051 8 bit (Mask ROM) 1980

Microchip PIC16C64 8 bit 1985

Motorola 68HC11 8 bit (on chip ADC) .

Intel 80C196 16 bit 1982

Atmel AT89C51 8 bit (Flash memory) .

Microchip PIC 16F877 8 bit (Flash memory + ADC) .

 Microcontroller
• A smaller computer
• On-chip RAM, ROM, I/O ports...
• Example：Motorola’s 6811, Intel’s
8051, Zilog’s Z8 and PIC 16X

CPU RAM ROM

A single chip
Serial
I/O Timer COM
Port
Port
Microcontroller
 ALU Timer/Counter I/O port

Accumulator
I/O port
Register(s)

Interrupt
circuits
Internal RAM Internal ROM

Clock circuit

Stack Pointer

Program Counter

Microcontroller Block diagram

Microprocessor vs. Microcontroller
Microprocessor
• CPU is stand-alone, RAM,
ROM, I/O, timer are
separate
• designer can decide on the
amount of ROM, RAM and
I/O ports.
• expansive
• versatility
• general-purpose
Microcontroller
• CPU, RAM, ROM, I/O and
timer are all on a single chip
• fix amount of on-chip ROM,
RAM, I/O ports
• for applications in which cost,
power and space are critical
• single-purpose
Microprocessor vs. Microcontroller
• RISC vs. CISC
• Reduced Instruction Set Computer (RISC)
• Compact, uniform instructions
• facilitate pipelining
• More lines of code
• poor memory footprint
• Allow effective compiler optimization
• Complex Instruction Set Computer (CISC)
• • Many addressing modes and instructions;
• • High code density.
• • Often require manual optimization of assembly code
• for embedded systems
 RISC CISC
1. Reduced Instruction Set Complex Instruction Set
2.Clock rate 20 – 200 Mhz Starts from 2 Mhz
3.Supports Register Few Registers will be found
Architecture More number of
4. Less Addressing modes Addressing modes
Powerful Data
More I/O Related manipulation
 Hardvard vs Von-neumann
Architecture
von Neumann Architecture
• Memory holds data, instructions.
• Central processing unit (CPU) fetches instructions from memory.
von Neumann vs. Harvard
• von Neumann
• Same memory holds data, instructions.
• A single set of address/data buses
betweenCPU and memory
• Harvard
• Separate memories for data and
instructions.
• Two sets of address/data buses
betweenCPU and memory
• von Neumann vs. Harvard
• Harvard makes it harder to write
• Self-modifying code (data values used as instructions)
• Harvard allows two simultaneous memory fetches.
• Harvard architectures are widely used because
Most DSPs use Harvard for streaming data
• The separation of program and data
memoriesgreater memory bandwidth  higher
performance for digital signal processing
• Speed is gained at the expense of more complex
electrical circuitry.
• Other examples: On chip cache of CPUs is divided into
an instruction cache and a data cache
 Embedded Electronic Systems
• All electric consumer products rely on digital
control
• Ex: washing machine, video recorders etc
• These products contain embedded electronic
systems
• High end cars have more than 80
processors and even a personal computer
has embedded processors in its keyboard,
mouse, screen, disk drives and so on.
• These processors are nothing but
microprocessors/microcontrollers
 What are the Different Kinds of
Controllers?
• PIC Microcontrollers
• Low power microcontroller
• 8051 microcontroller
 Comparison of Controllers
• PIC Microcontroller (C language)
– In built libraries for general use.
– Most commonly used.
– RISC CPU
– In built LCD driver, PWM, ADC
– Usually, internal registers must be modified to
perform various functions. (i.e. A/D, Timing,
PWM).
– In built EPROM, in addition to code memory
 Low power microcontrollers-MSP430

• 16 bit processor with a Von-Neuman Architecture,

designed for low power applications
• RISC CPU
• It is extremely easy to put the device into a low-
power mode
• No special instruction is needed
• The mode is controlled by bits in the status register
• Is awakened by an interrupt and returns
automatically to its low-power mode after handling
the interrupt
• Mixed signal processor
 MSP430 applications
• Alarm and Security (Smoke, Motion, Glass
Break Detector)
• Wireless Sensor Networks (Monitoring,
Asset Tracking)
• Portable Medical Applications
• MSP430 offers up to 70% lower power than the
PIC24F16KA102
• MSP430 has lower power modes than other MCUs
• MSP430 lasts 20+ Years on 1 battery
• As portability becomes a growing trend in
medical products, manufacturers are seeking
technologies that reduce the design complexity
and time in developing the finished product. In
most of these medical equipments, the actual
physiological signals are analog and require
signal conditioning techniques, such as
amplification and filtering, before they can be
measured, monitored, or displayed. The MSP430
microcontroller MCU offers a platform of ultra-
low-power processors with the high integration of
the complete signal chain that is required for
applications such as personal blood pressure
monitors, spirometers, pulsoximeters, and heart
rate monitors
 PIC microcontroller applications
• RPM meter
• speed control of DC and stepper motor
 8051 microcontroller hardware
• The 8051 microcontroller generic part
number includes a whole family of
microcontrollers that have numbers
ranging from 8031 to 8751 and are
available in N-channel NMOS and CMOS
construction in a variety of package types
• -40 pin IC
 Features unique to microcontrollers
The 8051 architecture consists of these specific
features
1. 8-bit CPU with registers A (the accumulator) and B
2. 16-bit program counter (PC) and Data
pointer(DPTR)
3. 8-bit program status word (PSW)
4. 8-bit stack pointer(SP)
5. Internal ROM or EPROM (8751) of 0(8031) to 4k
(8051)
6. Internal RAM of 128bytes
-4 register banks, each containing 8 registers
-16 bytes, which may be addressed at the bit level
-80 bytes of General purpose data memory
7. 32 input/output pins arranged as four 8-bit
ports:P0-P3
8. Two 16 bit timer/counters:T0 and T1
9. Full duplex serial data receiver/transmitter :SBUF
10. Control registers:TCON,TMOD,SCON,PCON,IP & IE
11. Two external and three internal interrupt sources
12. Oscillator and clock circuits
Programming model of 8051
• Programming model shows the 8051 as a
collection of 8 and 16 bit registers and 8-bit
memory locations
• Registers and memory locations can be made to
operate using the software instructions that are
incorporated as part of the design
• The model also includes special function registers
that make a microcomputer a microcontroller
PIN diagram
 The 8051 oscillator and clock
• The heart of the 8051 is the circuitry that
generates the clock pulses by which all internal
operations are synchronized

C1
18 XTAL2

Crystal or 8051 DIP

Ceramic Resonator

19 XTAL1
C2
• Pins XTAL1 and XTAL2 are provided for
connecting a resonant network to form an
oscillator
• Typically quartz crystal and capacitors are
employed(previous figure)
• Crystal frequency is the basic internal clock
frequency of the microcontroller
• Varies from 1MHz to 16 MHz
• Minimum frequencies imply that some internal
memories are dynamic and must always operate
above a minimum frequency or data will be lost
Oscill P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
ator
freq
f
state1 state2 state3 state4 state5 state6

One machine cycle

ALE

8051 timing
• Ceramic resonators may be used as a low-cost
alternative to crystal resonators
• Decreases in frequency stability and accuracy
make the ceramic resonator a poor choice if high
speed serial data communication with other
systems, or critical timing, is to be done
• The oscillator formed by the crystal, capacitors
and on-chip inverter generates a pulse train at
the frequency of the crystal is shown in the figure
• The clock frequency, f establishes the smallest
interval of time within the microcontroller, called
the pulse P, time
• The smallest interval of time to accomplish any
simple instruction, or part of a complex
instruction is the machine cycle
• One machine cycle=6 states
• A state is the basic time interval for discrete
operations of the microcontroller such as fetching
an opcode byte, decoding an opcode, executign
an opcode, or writing a data byte
• Two oscillator pulses define each state
• Program instructions may require one, two or
four machine cycles to be executed, depending
on the type of instruction
• Instructions are fetched and executed by the
microcontroller automatically, beginning with the
instruction located at ROM memory address
0000h at the time the microcontroller is first
reset
• To calculate the time any particular instruction will
take to be executed, find the number of cycles, C
• The time to execute that instruction is then found
by multiplying C by 12 and dividing the product by
the crystal frequency
• Tinst =CX12d/crystal frequency
• Ex: if the crystal frequency is 16Mhz, then the time
to execute an ADD A,R1 one-cycle instruction is
.75microseconds
• A 12Mhz crystal yields the convenient time of
1microsecond per cycle
• An 11.0592Mhz crystal, yields a cycle frequency of
921.6Khz, which can be divided evenly by the
standard communication baud rates of
19200,9600,4800,2400,1200 and 300hertz
• There are 2 ALE pulses per machine cycle(prev,
fig)
• The ALE pulse, which is primarily used as a
timing pulse for external memory access,
indicates when every instruction byte is fetched
• 2 bytes of a single instruction may thus be
fetched and executed in one machine cycle
• However single byte instructions are not
executed in a half cycle
• Single byte instructions “throw-away” the second
byte(which is the first byte of the next
instruction)
• The next instruction is then fetched in the
following cycle
 Program counter and data pointer
• 8051 contains two 16-bit registers: the program
counter(PC) and the data pointer(DPTR)
• Each is used to hold the address of a byte in
memory
• Program instruction bytes are fetched from
locations ain memory that are addressed by the
PC
• Program ROM may be on the chip at addresses
0000h to 0FFFh, external to the chip for
addresses that exceed 0FFFh, or totally external
for all addresses from 0000h to FFFFh
• The PC is automatically incremented after every
instruction byte is fetched and may also be
altered by certain instructions
• DPTR is made up of two 8 bit registers, DPH and
DPL which are used to furnish memory addresses
for internal and external code access and
external data access
• DPTR is under the control of program instructions
and can be specified by its 16 bit name, DPTR, or
by each individual byte name, DPH and DPL
• DPTR doesn't have a single internal address
• DPL and DPH are each assigned an address
 A and B CPU registers
• 8051 contains 34 general-purpose, or working
registers
• Two of these, registers A and B hold results of many
instructions, particularly math and logical operations,
of the 8051 CPU
• The other 32 are arranged as part of the internal
RAM in four banks, B0-B3, of 8 registers
• The A(accumulator) register is the more versatile of
the two CPU registers and is used for many
operations, including addition, subtraction, integer
multiplication and division, and Boolean bit
manipulations.
• The A register is also used for all data transfers
between 8051 and an external memory
• The B register is used with the A register for
multiplication and division operations and has no
other function other than as a location where
data may be stored
 Flag & the Program status Word(PSW)
• Flags-1 bit registers provided to store the results of
certain program instructions
• Other instructions can test the condition of the flags
and make decisions based on the flag states
• PSW and PCON registers are used to address these
flags
• 8051 has 4 math flags that respond automatically to
the outcomes of math operations and 3 general
purpose user flags that can be set to 1 or cleared to
0 by the programmer as desired
• The math flags include C, AC,OV and P
• User flags are F0,GF0,GF1
• They are general purpose flags that may be used
by the programmer to record some event in the
program
• All of the flags can be set and cleared by the
programmer at will
• The math flags, however, are also affected by
math operations
 PSW

7 6 5 4 3 2 1 0
PSW CY AC F0 RS1 RS0 OV - P

Carry flag Parity flag

Auxiliary Carry flag Overflow flag
Flag 0 Registar Bank
Registar Bank Select bit 0
Select bit 1

• Auxiliary Carry flag is used for BCD operations

• Flag 0 is available to user for general purposes
• The contest of (RS1, RS0) enable working register banks as follows: 00 - Bank 0
[0x00-0x07], 01 - Bank 1 [0x08-0x0f],
10 - Bank 2 [ 0x10-0x17], 11 - Bank 3 [0x18-0x1F]
• The PSW contains the math flags, user program
flag F0 and the register select bits that identify
which of the 4 general purpose register banks is
currently in use by the program
• The remaining two user flags, GF0 and GF1 are
stored in PCON register
 Internal memory
• A functioning computer must have memory for
storing the program codes , commonly ROM, and
the RAM memory for variable data that can be
altered as the program runs
• The 8051 has internal RAM and ROM memory for
these functions
• Additional memory can be added externally using
suitable circuits
• The 8051 has a Harvard architecture which uses
the same address, in different memories, for code
and data.
• Internal circuitry accesses the correct memory
based on the nature of the operation in progress
 Internal RAM
• The 128-byte internal RAM, is organized into 3
distinct areas
1. 32 bytes from address 00h-1Fh that make up 32
working registers organized as 4 banks of 8
registers each
• The four register banks are numbered 0-3 and are
made up of 8 registers named R0-R7
• Each register can be addressed by name (when its
bank is selected) or by its RAM address
• Thus R0 of bank 3 is R0(if bank 3 is currently
selected) or address 18h (whether bank 3 is
selected or not)
• Bits RS0 and RS1 in the PSW determine which bank
of registers is currently in use at any time when the
program is running
• Register banks not selected can be used as general-
purpose RAM, Bank0 is selected on reset
2. A bit addressable area of 16bytes occupies RAM
byte addresses 20h to 2Fh, forming a total of 128
addressable bits
• An addressable bit may be specified by its bit
address of 00-7fh, or 8 bits may form any byte
address from 20h to 2fh.
• Ex: bit address 4fh is also bit 7 of byte address 29h
3. A general purpose RAM area above the bit area,
from 30h to 7fh, addressable as bytes.
Internal RAM structure
 Working registers
1F
Four Register Banks
Each bank has R0-R7
Bank 3

18
17

Bank 2

10
0F

Bank 1

08

Bank 0
 Bit Addressable Memory
2F 7F 78
20h – 2Fh (16 locations X 8-bits
2E
= 128 bits)
2D
2C Bit addressing:
2B mov C, 1Ah
2A or
29 mov C, 23h.2
28
27
26
25
24
23 1A
22 10
21 0F 08
20 07 06 05 04 03 02 01 00
 General Purpose registers
Byte
address
7F

30
 The stack and the stack pointer
• Refers to an area of internal RAM that is used in
conjunction with certain opcodes to store and
retrieve data quickly
• The 8-bit stack pointer (SP) register is used to
hold an internal RAM address called the Top of
the Stack
• The address held in the SP register is the location
in internal RAM where the last byte of data was
stored by a stack operation
• When data is to be placed on the stack, SP
increments before storing data on the stack so
that the stack grows up as data is stored
• As data is retrieved from the stack, the byte is
read from the stack, and then the SP decrements
to point to the next available byte of stored data
 Operation of the stack and SP
CPU CPU
action action

SP=0A Stored Address 0A Get data SP=0A

data
Stored
SP=09 Address 09 Get data SP=09
data

SP=08 Stored Address 08 Get data SP=08

data

SP=07 Address 07 SP=07

Storing data on the stack Internal RAM Getting data from the stack
• The SP is set to 07h when the 8051 is reset and
can be changed to any internal RAM address by
the programmer, using a data move command.
• The stack is limited in height to the size of the
internal RAM
• The stack has the potential to overwrite valuable
data in the register banks, bit addressable RAM
and scratch –pad RAM areas.
• The programmer is responsible for making sure
the stack doesn’t grow beyond predefined bounds
• The stack is normally placed high in internal RAM,
by an appropriate choice of the number placed in
the SP register, to avoid conflict with the register,
bit and the scratch-pad internal RAM areas
 Special function registers
• The 8051 operations that do not use the internal
128-byte RAM addresses from 00h-7Fh are done by
a group of specific internal registers, each called a
Special function register(SFR), which may be
addressed much like internal RAM, using addresses
from 80h-FFh
• Some SFRs are bit addressable.
• This feature allows the programmer to change only
what needs to be altered, leaving the remaining bits
in that SFR unchanged
• Not all of the addresses from 80h-FFh are used for
SFRs, and attempting to use an address that is not
defined, or empty, results in unpredictable results.
 SFRs and their addresses

0 1 2 3 4 5 6 7
F8 FF
F0 B F7
E8 EF
E0 ACC E7
D8 DF
D0 PSW D7
C8 CF
C0 C7
B8 IP BF
B0 P3 B7
A8 IE AF
A0 P2 A7
98 SCON SBUF 9F
90 T1 97
88 TCON TMOD TL0 TL1 TH0 TH1 8F
80 T0 SP DPL DPH PCON 87
• PC is not part of the SFR and has no internal RAM
address
• SFRs are named in certain op codes by their
functional names, such as A or TH0, and are
referenced by other op codes by their addresses,
such as 0E0h or 8ch
 Internal ROM
• 8051 is organized so that data memory and
program code memory can be in two entirely
different physical memory entities
• Each has the same address ranges
• Block of internal program code, contained in an
internal ROM, occupies code address space of
0000h-0FFFh
• The PC is ordinarily used to address program code
bytes from addresses 0000h-FFFFh
• When the Program address exceeds 0FFFh, the
internal ROM capacity, 8051 automatically fetches
the code bytes from external program memory
• Code bytes can also be fetched exclusively from an
external memory by connecting the external access
pin (EA) to ground
 Input/output pins, ports and circuits

• One major feature of a microcontroller is the

versatility built into the i/p/o/p(I/O) circuits that
connect the 8051 to the outside world
• 8051 is a 40 pin IC and 24 of these pins may be
used as I/O pins
 Hardware Structure of I/O Pin

• Each pin of I/O ports

– Internal CPU bus：communicate with CPU
– A D latch store the value of this pin
• D latch is controlled by “Write to latch”
– Write to latch＝1：write data into the D latch
– 2 Tri-state buffer：
• TB1: controlled by “Read pin”
– Read pin＝1：really read the data present at the pin
• TB2: controlled by “Read latch”
– Read latch＝1：read value from internal latch
– A transistor M1 gate
• Gate=0: open
• Gate=1: close
D Latch:
• Port 0 pins may serve as inputs, outputs, or when
used together, as a bidirectional low-order address
and data bus for external memory
• Ex: When a pin is to be used as an input, a 1 must
be written to the corresponding port 0 latch by the
program, thus turning both the transistors off,
which in turn causes the pin to “float” in a high
impedance state, and the pin is essentially
connected to the input buffer
• When used as an output, the pin latches that are
programmed to a 0 will turn on the lower FET,
grounding the pin
• All latches that are programmed to a 1 still float,
thus external pullup resistors will be needed to
supply a logic high when using port 0 as an output.
• When port 0 is used as an address bus to
external memory, internal control signals switch
the address lines to the gates of the FETs.
• A logic 1 on an address bit will turn the upper
FET on and the lower FET off to provide a logic
high at the pin.
• When the address bit is a 0, the lower FET is on
and the upper FET off to provide a logic low at
the pin
• After the address has been formed and latched
into the external circuits by the ALE pulse, the
bus is turned around to become a data bus
• Port 0 now reads data from the external memory
and must be configured as an input, so a logic 1
is automatically written by internal control logic
to all port 0 latches
 Port 1
• Port1 pins have no dual functions
• Therefore, the output latch is connected directly to
the gate of the lower FET, which has an FET
circuit(internal pullup as an active pullup load)
• When used as an input, a 1 is written to the latch,
turning the lower FET off; the pin and the input to
the pin buffer are pulled high by the FET load
• An external circuit can overcome the high-speed
pullup and drive the pin low to input a 0 or leave the
input high for a 1
• If used as an output, the latches containing a 1 can
drive the input of an external circuit high through
pullup
• If a 0 us written to the latch, the lower FET is on, the
pullup is off, and the pin can drive the input of the
external circuit low
 A Pin of Port 1

Read latch Vcc

TB2
Load(L1)

Internal CPU D Q P1.X

bus P1.X pin

Write to latch Clk Q M1

TB1
Read pin P0.x
8051 IC
 Writing “1” to Output Pin P1.X

Read latch Vcc

TB2
Load(L1) 2. output pin is
1. write a 1 to the pin Vcc
1 P1.X
Internal CPU D Q
bus P1.X pin
0 output 1
Write to latch Clk Q M1

TB1
Read pin

8051 IC
 Writing “0” to Output Pin P1.X

Read latch Vcc

TB2
Load(L1) 2. output pin is
1. write a 0 to the pin ground
0 P1.X
Internal CPU D Q
bus P1.X pin
1 output 0
Write to latch Clk Q M1

TB1
Read pin

8051 IC
 Reading “High” at Input Pin

Read latch Vcc 2. MOV A,P1

TB2 external pin=High
1. write a 1 to the pin MOV Load(L1)
P1,#0FFH

1 1 P1.X pin
Internal CPU bus D Q
P1.X
0 M1
Write to latch Clk Q

TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1
8051 IC
 Reading “Low” at Input Pin

Read latch Vcc 2. MOV A,P1

TB2
1. write a 1 to the pin Load(L1) external pin=Low
MOV P1,#0FFH
1 0 P1.X pin
Internal CPU bus D Q
P1.X
0 M1
Write to latch Clk Q

TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1
8051 IC
• To aid in speeding up switching times when the
pin is used as an output, the internal FET pullup
has another FET in parallel with it
• The second FET is turned on for 2 oscillator time
periods during a low-to-high transition on the pin
• This arrangement provides a low impedance path
to the positive voltage supply to help reduce rise
times in charging any parasitic capacitances in
the external circuitry
 Port2
• Port 2 may be used as in input/output port
similar in operation to port1
• The alternate use of port 2 is to supply a high-
order address byte in conjunction with the port 0
low-order byte to address external memory
• Port2 pins are momentarily changed by the
address control signals when supplying the high
byte of a 16-bit address
• Port 2 latches remain stable when external
memory is addressed, as they do not have to be
turned around for data input as is the case for
port 0
 Port 3
• Port3 is an input/output similar to port1
• The input and output functions can be programmed
under the control of the P3 latches or under the
control of various other special function registers
• The port3 alternate uses are shown below.
Pin Alternate Use SFR
P3.0-RXD Serial data input SBUF
P3.1-TXD Serial data output SBUF
P3.2-INT0 External Interrupt0 TCON.1
P3.3-INT1 External interrupt1 TCON.3
P3.4-T0 External timer0 input TMOD
P3.5-T1 External timer1 input TMOD
P3.6-WR External memory write ---
pulse
P3.7-RD External memory read pulse ---
 External Memory
• The system designer is not limited by the amount
of internal RAM and ROM available on chip
• Two separate external memory spaces are made
available by the 16-bit PC and DPTR and by
different control pins for enabling external ROM
and RAM chips
• Internal control circuitry accesses the correct
physical memory, depending on the machine
cycle state and the opcode being executed
• External RAM, which is accessed by the DPTR,
may also be needed when 128 bytes of internal
data storage is not sufficient
• External RAM, upto 64k, may also be added to
any chip in the 8051 family
• There are several reasons for adding external
memory, particularly Program Memory, when
applying the 8051 in a system.
• When project is in the prototype stage, having a
masked internal ROM for each program “try” is
prohibitive.
• To help the programmer the manufacturers make
available an EPROM version, the 8751, which has
4K of on-chip EPROM that may be programmed
and erased as needed as the program is
developed
• External program memory is fetched if either of
the following two conditions are satisfied.
External program memory is fetched if either of
the following two conditions are satisfied.
• EA is low. The microcontroller by default starts
searching for program from external program
memory.
• PC is higher than FFFH for 8051 or 1FFFH for 8052.
• PSEN tells the outside world whether the external
memory fetched is program memory or data
memory.
• EA is user configurable.
• PSEN is processor controlled