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Shift Registers

Presented by

Dr. J. Nelson Raja


Assistant Professor
Department of Computer Application
Arul Anandar College ,Karumathur
Madurai
Shift Register

 A register is simply a group of flip-flops and Each flip-flop stores one bit
data.

 For instance, a register used to store an 8-bit binary number must have
eight flip-flops.

 A shift register is a group of flip-flops set up in a linear fashion with their


inputs and outputs connected together in such a way that the data is
shifted from one device to another when the circuit is active.

 It allows each of the flip-flops to pass the stored information to its


adjacent neighbour.
Shift Register

 The bits in a binary number (let's call them the data) can be moved
from one place to another in either of two ways.

 The first method involves shifting the data 1 bit at a time in a serial
fashion, beginning with either the most significant bit (MSB) or the least
significant bit (LSB). This technique is referred to as serial shifting.

 The second method involves shifting all the data bits simultaneously and
is referred to as parallel shifting.
Types of Shift Register

1. Serial-in, Serial-out
2. Serial-in, Parallel-out
3. Parallel-in, Serial-out
4. Parallel-in, Parallel-out
Serial In - Serial Out Shift Registers

The serial in/serial out shift register accepts data serially ie, one bit
at a time on a single line. It produces the stored information on its
output in serial form.

A basic four-bit shift register can be constructed using four D flip-


flops, as shown in Figure.
The operation of the circuit is as follows
1. The register is first cleared, forcing all four
outputs to zero.
2. The input data is then applied sequentially to
the D input of the first flip-flop on the left
(FF0).
3. During each clock pulse, one bit is transmitted
from left to right.
4. Assume a data word to be 1011. The least
significant bit of the data has to be shifted
through the register from FF0 to FF3.
5. In order to get the data out of the register, they
must be shifted out serially.
6. The data is loaded to the register when the
control line is HIGH (ie WRITE).
7. The data can be shifted out of the register
when the control line is LOW (ie READ).
Serial In - Parallel Out Shift Registers

Serial In - Parallel Out Shift Registers is loaded


with data in serial form ie. one bit at a time and
the stored data is available at the output in
parallel form.

This is easily accomplished by connecting the


output of each flip-flop to an output pin. For
instance, an 4-bit shift register would have eight
output lines-one for each flip-flop in the register.

Q0, Q1, Q2, Q3 are outputs.


Q0, Q1, Q2, Q3 are outputs
Parallel In – Serial Out Shift Register

In Parallel-In Serial-Out Shift Register, the input data is loaded


parallel into the register and the output shift is serial one ie. one bit
at a time under clock control.

A four-bit parallel in - serial out shift register is shown below. The


circuit uses D flip-flops and NAND gates for entering data (ie writing)
to the register.
Parallel In – Serial Out Shift Register

D0, D1, D2 and D3 are the parallel inputs, where D0 is the most
significant bit and D3 is the least significant bit.

To write data in, the mode control line is taken to LOW and the data is
clocked in. The data can be shifted when the mode control line is HIGH
as SHIFT is active high.
Parallel-In Serial-Out Shift Register
Parallel In – Parallel out Shift Register

 In Parallel-in to Parallel-out Shift Register, data can be shifted either into


or out of the register in parallel.

 ie. The parallel data is loaded simultaneously into the register, and
transferred together to their respective outputs by the same clock pulse.

 The following circuit is a four-bit parallel in - parallel out shift register


constructed by D flip-flops.

 The D's (D0, D1, D2, D3) are the parallel inputs and the Q's (Q0, Q1, Q2,
Q3) are the parallel outputs. Once the register is clocked, all the data at
the D inputs appear at the corresponding Q outputs simultaneously.
Parallel In - Parallel Out Shift Register

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