Field-Effect Transistor

INTRODUCTION

 The invention of the BJT has brought a great twist in the modern era of
semiconductor technology. This device, along with its field-effect
counterpart, known as the field-effect transistor (FET), has had a huge
impact on virtually every area of modern life.

 Practical field-effect transistors were first made in the form of JFET in

1953 and MOSFET in 1963.

 The field-effect transistor has taken various forms like that

 The junction field-effect transistor (JFET),
 The metal semiconductor field-effect transistor (MESFET),
 The metal-insulator-semiconductor field-effect transistor (MISFET),
 The metal-oxide-semiconductor field-effect transistor (MOSFET).
 Different types of FETs
 Junction FET (JFET)
 Metal-Oxide-Semiconductor FET (MOSFET)
 D-MOSFET - Depletion Mode MOSFET
 E- MOSFET - Enhancement Mode MOSFET

Current Controlled vs Voltage Controlled Devices

Kulwant Singh, M.Tech, Ph.D 11/11/2018

THE FIELD-EFFECT TRANSISTOR
 The FET is a single carrier device and is often called the unipolar transistor
because the carriers involved in the operation are either electrons or holes.
 The FET is also a semiconductor device in which the output quantity is
controlled by an electric field, which is often the input quantity.
 The phenomenon where the conductivity of the semiconductor is
modulated by an electric field applied normally to the surface of the
semiconductor is called field effect, and this principle is brought into
operation by extending the depletion region deep into the bulk of the
semiconductor.
 Junction Field-effect Transistor (JFET):- In a junction FET, the control
voltage modulates the depletion width of a reverse-biased p –n junction
which, in turn, varies with the various parameters of the device.
 Insulated Gate Field-effect Transistor (IGFET):- The IGFET is also
called the metal-oxide-semiconductor field-effect transistor (MOSFET). In this,
the metal gate electrode is separated from the semiconductor by an insulator.
 Metal-semiconductor Field-effect Transistor (MESFET):- If the MOS
junction is replaced by a direct metal-semiconductor contact, i.e., a Schottky
barrier, it is called metal-semiconductor FET (MESFET). A MESFET is similar
to a JFET except for the following differences:(i) It has a single gate (ii) The
gate is formed by a metal-semiconductor junction
 CONSTRUCTION OF THE JFET
 The JFET is a three-terminal device whose one terminal is capable of
controlling the current between the other two.
 In JFETs, the width of a junction is used to control the effective cross-
sectional area of the channel that conducts current.
 JFETs are basically of two types: n-channel and p-channel.

Construction of n-channel JFET

 CONSTRUCTION OF THE JFET
 The n-channel JFET consists of a uniformly doped n-type silicon
semiconductor bar with ohmic contacts at both ends and semiconductor
junctions made on either sides of the bar.

 The top portion of the n-type channel is connected through the ohmic
contact to a terminal called the drain (D) while the lower end is connected
to the terminal referred to as the source (S ).

 The two p-type materials, fabricated on the two sides, are connected
together and then to the third terminal called gate (G).

 The source terminal gets its name from the fact that the carriers
contributing to the current flow move out from the external circuit into the
semiconductor at this electrode.

 The carriers travel through the bulk of the semiconductor and are
subsequently collected at the drain electrode.

 The gate is called so because it controls the flow of charges though the
bulk.
 CONSTRUCTION OF THE JFET
 With proper biasing of the device, current is allowed to flow from the
source and gets collected at the drain terminal of the bar.
 As the drain current (ID) flows through the channel, a reverse-bias
between the two p-regions and the channel reduces the effective width of
the channel.
 As the effective width of the conducting channel has a striking effect on
the resistance of the channel, the current flowing through it also varies
correspondingly.
 The electrons in the n-region move from the source to the drain region;
they are carried by majority carriers that drift through the channel.
 The majority carriers enter the channel region through the source
terminal and leave the channel through the drain terminal, in agreement
with the naming of the drain and the source terminals.
 In the absence of any applied potentials at the two p –n junctions, the
JFET is under no-bias condition.
 The result is a depletion region at each junction that resembles the
same region of a junction diode under no-bias conditions.
 For normal operation, the current enters the channel through the drain
and as it flows through the channel the voltage drop constantly decreases.
 This can be a linear variation for low values of current.
 CONSTRUCTION OF THE JFET
 The FETs have considerably higher input impedance as compared to
BJTs.
 It is evident that the control voltage is applied to a reverse-biased
junction. So, the FET has a negative temperature coefficient at high
current levels.
 This characteristic leads to a more uniform temperature distribution
over the device area and prevents the FET from thermal runaway, which
is a major point of concern in bipolar transistors.
 The device is thermally stable, even when the active area is large and
when many such devices are connected in parallel.
 Because FETs are unipolar devices, they hardly suffer from any
minority-shortage effects, and thus, have higher switching speeds and
higher cut off frequency.
 This makes their operation rather smooth. In addition to this they are
square-law devices, i.e., inter-modulation and cross-modulation products
are much smaller than those of a bipolar transistors.
 BIASING OF THE JFET
 Let us now study the operation of the device with respect to the
characteristics of an n-channel JFET.
 We shall consider two different cases in this regard.
 When VGS 0 V, VDS some positive value: a positive voltage VDS has
been applied across the channel and the gate has been connected directly
to the source to establish the condition VGS 0 V.

State of the device with zero source–gate voltage

and positive drain–source voltage
Actually in FET (field effect transistor) ,the
drain to source current is controlled by the
width of the channel. The channel width is
again controlled by the electric field
produced at gate ( due to capacitive
effects). The electric field can be produced
at the gate by applying some external
voltage.
 Shockley’s Equation

FET Transfer Characteristics

THE FIELD-EFFECT TRANSISTOR
Comparison between the BJT and the FET
MOSFET History (Very Short!)

 First Patents:
 1935
 Variable Capacitor Proposed:
 1959
 Silicon MOS:
 1960
 Clean PMOS, NMOS:
 Late 1960s, big growth!
 Switch to CMOS (Complementary metal oxide semiconductor):
 1980s
 ?????????????
 MOSFETs

MOSFETs have characteristics similar to JFETs and additional

characteristics (????) that make then very useful

• Depletion mode MOSFET (D-MOSFET)

• Operates in Depletion mode the same way as a JFET when VGS  0

• Enhancement Mode MOSFET (E-MOSFET)

• Operates in Enhancement mode
• IDSS = 0 until VGS > VT (threshold voltage)

Kulwant Singh, M.Tech, Ph.D 11/11/2018

 Structure: n-channel MOSFET (NMOS)

gate: metal or heavily doped poly-Si

G
(bulk or body source IG=0 drain
substrate) B S D
ID=IS
y IS

metal
oxide

n+ n+
p
x

W
L
Kulwant Singh, M.Tech, Ph.D 11/11/2018
MOSFET Future (One Part of)

 International Technology Roadmap for Semiconductors, 2008

update.
 Look at size, manufacturing technique.
From Intel
 CMOS technology nodes and predicted end of CMOS down-scaling with
possible alternatives (nanotubes and nanowires) for post-2015
nanotechnology

Kulwant Singh, M.Tech, Ph.D

Circuit Symbol (NMOS)
enhancement-type: no channel at zero gate voltage

D
ID= IS

G B (IB=0, should be reverse biased)

IG= 0

IS G-Gate
D-Drain
S S-Source
B-Substrate or Body
 Electron affinity

Kulwant Singh, M.Tech, Ph.D 11/11/2018

Kulwant Singh, M.Tech, Ph.D 11/11/2018
The built-in potential difference across this MOS system is -

If a voltage corresponding to this potential difference is applied externally between

the gate and the substrate, the bending of the energy bands near the surface can be
compensated, i.e., the energy bands become "flat." Thus, the voltage defined by

is called the flat-band voltage.

Kulwant Singh, M.Tech, Ph.D 11/11/2018
The cross-sectional view and the energy band diagram of the MOS structure
operating in accumulation region.

Kulwant Singh, M.Tech, Ph.D 11/11/2018

 negatively charged
fixed acceptor ions

The cross-sectional view and the energy band diagram of the MOS structure
operating in depletion mode, under small gate bias.

Kulwant Singh, M.Tech, Ph.D 11/11/2018

The cross-sectional view and the energy band diagram of the MOS structure in
surface inversion, under larger gate bias voltage.

Kulwant Singh, M.Tech, Ph.D 11/11/2018

Flat bands! For this choice of materials, VGS<0 n+pn+ structure  ID ~ 0

gate
G
body source drain
B S - + D
VD=Vs

n++
oxide

n+ n+
p

W
L
Flatbands < VGS < VT (Includes VGS=0 here). n+-depletion-n+ structure  ID ~ 0

gate
G
body source drain
B S - + D
VD=Vs
+++
n++
oxide

n+ n+
p

W
L
 VGS > VT n+-n-n+ structure  inversion

gate
G
body source drain
B S - + D

+++
+++
+++
n++
oxide
-----
n+ n+
p

W
L
 Band diagram of the MOS structure underneath the gate, at surface inversion.
Notice the band bending by at the surface.

The value of the gate-to-source voltage VGS needed to cause surface

inversion (to create the conducting channel) is called the threshold voltage
Kulwant Singh, M.Tech, Ph.D 11/11/2018
Threshold Voltage Definition

VGS = VT when the carrier

concentration in the channel
is equal to the carrier
concentration in the bulk
silicon.

Mathematically, this occurs

when fs=2ff ,
where fs is called the
surface potential
Triode Region
A voltage-controlled resistor @small VDS

B S D
- +
ID
+++ VGS1>Vt
+++
increasing
metal
- oxide
- - -
VGS
n+ n+
p

B S -+ D

+++ VGS2>VGS1
+++
+++
metal G
- -oxide
- - --
n+ n+
p
cut-off VDS
B S -+ D
0.1 v
+++ VGS3>VGS2
+++
+++ +++ Increasing VGS puts more
metal

n+
- - -oxide
------
n+ charge in the channel, allowing
p
more drain current to flow
Saturation Region occurs at large V DS

As the drain voltage increases, the difference in

voltage between the drain and the gate becomes
smaller. At some point, the difference is too small
to maintain the channel near the drain  pinch-off
gate
G
body source drain
+
B S - D
VDS large
+++
+++
+++
metal
oxide

n+ n+
p
Saturation Region occurs at large V DS

The saturation region is when the MOSFET

experiences pinch-off.
Pinch-off occurs when VG - VD is less than VT.
gate
G
body source drain
+
B S - D
VDS large
+++
+++
+++
metal
oxide

n+ n+
p
Saturation Region occurs at large V DS

VGS - VDS < VT or VGD < VT

VDS > VGS - VT

gate
G
body source drain
+
B S - D
VD>>Vs
+++
+++
+++
metal
oxide

n+ n+
p
MOSFET Operation: A Qualitative View

(b)
(a)

(c)
Cross-sectional view of an n-channel (nMOS) transistor, (a) operating in the linear
region, (b) operating at the edge of saturation, and (c) operating beyond saturation.

Kulwant Singh, M.Tech, Ph.D 11/11/2018

MOSFET Current-Voltage Characteristics

Cross-sectional view of an n-channel transistor, operating in linear region.

Kulwant Singh, M.Tech, Ph.D 11/11/2018

Basic current-voltage characteristics of an n-channel MOS transistor.

Kulwant Singh, M.Tech, Ph.D 11/11/2018

Drain current of the n-channel MOS transistor as a function of the gate-to-source
voltage VGS, with VDS > VDSAT (transistor in saturation).
Kulwant Singh, M.Tech, Ph.D 11/11/2018
Sketching the transfer characteristics for an n-channel enhancement type
MOSFET from the drain characteristics (Considering Threshold voltage effect)

Kulwant Singh, M.Tech, Ph.D 11/11/2018

 Transconductance parameter/2 = kn

Here, λ is an empirical model parameter, and is called the channel length modulation
coefficient.
Kulwant Singh, M.Tech, Ph.D 11/11/2018
 Transconductance parameter/2 = kp

Here, λ is an empirical model parameter, and is called the channel length modulation
coefficient.

Kulwant Singh, M.Tech, Ph.D 11/11/2018

 Channel Length Modulation

Note that this current equation corresponds to a MOSFET with effective channel
length L', operating in saturation. Thus, above equation accounts for the actual
shortening of the channel, also called channel length modulation.

Here, λ is an empirical model parameter, and is called the channel length

modulation coefficient.

Kulwant Singh, M.Tech, Ph.D 11/11/2018

Current-voltage characteristics of an n-channel MOS transistor, including the
channel length modulation effect.

Kulwant Singh, M.Tech, Ph.D 11/11/2018