 Instruction format

 Instruction fields
 Opcode and Operands
 Instruction execution stages/flow
 CPU registers
 Data transfer between CPU registers
 Design of Common Bus System using
multiplexers

Computer Architecture~ Fall 2018 1

 Computer System Architecture, 3rd ed. by
Morris Mano, (Chapter 4 & 5)

Computer Architecture~ Fall 2018 2

 Opcode Operand

 Opcode field specifies the operation type

 Operand field specifies the operand to be
operated
 Number of bits in Opcode field depends
upon?
 Number of bits in Operand field depends
upon?
 There can be more than one operands?

Computer Architecture~ Fall 2018 3

 Consider, a system has 16 registers and has
32bytes of memory.
 Each register is 64-bit wide
 System is capable of performing 16
operations.
 How many bits should be in Opcode and
Operand fields?
 What will be the instruction length?

Opcode Operand

Computer Architecture~ Fall 2018 4

 Consider a memory unit, 4096*16.
 1 bit is reserved to address operands using
memory direct or memory indirect addressing
modes.
 3 bits are reserved for opcode field.

 How many bits are required for address field?

 What will be the total length of instruction?

Opcode Operand

Computer Architecture~ Fall 2018 5

 Von Neumann architecture
◦ Single bus for data transfer and instruction fetches
◦ Instructions and data reside in same memory
◦ General purpose computers

 Harvard architecture
◦ Separate memories for instruction and data
◦ Dedicated processors, DSP processor

Computer Architecture~ Fall 2018 6

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How many registers are
needed to process this
instruction execution flow?

Computer Architecture~ Fall 2018 8

 Program Counter (PC)
 Address Register (AR)
 Instruction Register (IR)
 Data Register (DR)
 Accumulator Register (AC)

 Temporary Register (TR)

 Input Register (INPR)
 Output Register (OUTR)

Computer Architecture~ Fall 2018 9

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 Transfer data from R1 to R2 when control
signal P is 1?
𝑃: 𝑅2 ← 𝑅1

Computer Architecture~ Fall 2018 12