Calibre UG

Programmable Configurations
• Read Only Memory (ROM) –

– a fixed array of AND gates and a programmable array of OR gates
• Programmable Array Logic (PAL) –
– a programmable array of AND gates feeding a fixed array of OR
gates.
• Programmable Logic Array (PLA) –
– a programmable array of AND gates feeding a programmable array
of OR gates.
• Complex Programmable Logic Device (CPLD) /Field-
Programmable Gate Array (FPGA) –
– complex enough to be called “architectures”
KU College of Engineering
Lecture 9 Elec 204: Digital Systems Design
1
ROM, PAL and PLA Configurations
Fixed Programmable
Inputs Programmable Outputs
AND array
Connections OR array
(decoder)
(a) Programmable read-only memory (PROM)
Programmable Programmable Fixed

Inputs Outputs
Connections AND array OR array
(b) Programmable array logic (PAL) device
Programmable Programmable Programmable Programmable

Inputs Outputs
Connections AND array Connections OR array
(c) Programmable logic array (PLA) device

2
Read Only Memory
• Read Only Memories (ROM) or Programmable Read Only
Memories (PROM) have:
– N input lines,
– M output lines, and
– 2N decoded minterms.
• Fixed AND array with 2N outputs implementing all N-literal
minterms.
• Programmable OR Array with M outputs lines to form up to
M sum of minterm expressions.
• A program for a ROM or PROM is simply a multiple-output
truth table
– If a 1 entry, a connection is made to the corresponding minterm for the
corresponding output
– If a 0, no connection is made
3
Read Only Memory Example
• Example: A 8 X 4 ROM (N = 3 input lines, M= 4 output lines)
• The fixed "AND" array is a D7 X X X
“decoder” with 3 inputs and 8 D6
outputs implementing minterms. D5 X X
D4 X
• The programmable "OR“
A A2 D3 X
array uses a single line to D2
B A1 D1 X X
represent all inputs to an X
C A0 D0
OR gate. An “X” in the
array corresponds to attaching the
minterm to the OR
• Read Example: For input (A2,A1,A0)
= 011, output is (F3,F2,F1,F0 ) = 0011. F3 F2 F1 F0
• What are functions F3, F2 , F1 and F0 in terms of (A2, A1, A0)?
4
Programmable Array Logic (PAL)
• The PAL is the opposite of the ROM, having a programmable set
of ANDs combined with fixed ORs.
• Disadvantage
– ROM guaranteed to implement any M functions of N
inputs. PAL may have too few inputs to the OR gates.
• Advantages
– For given internal complexity, a PAL can have larger N and M
– Some PALs have outputs that can be complemented, adding POS
functions
– No multilevel circuit implementations in ROM (without external
connections from output to input). PAL has
outputs from OR terms as internal inputs to all AND
terms, making implementation of multi-level circuits easier.
5
AND gates inputs
Programmable Array Logic 0 1 2 3 4 5 6 7 8 9
X
Product 1
Example term
2
X X
F1
3
• 4-input, 3-output PAL with
I 1= A
fixed, 3-input OR terms X X X
4
• What are the equations for F1 X X
5 F2
through F4?
X X
F1 = C’ + A’B’ 6
I2 = B
F2 = A’BC’ + AC + AB’ X X
7
F3 = AD + BD + F1
X X
F4 = AB + CD + F1’ 8 F3
X
9
I3 = C
X X
10
X X
11 F4
X
12
I4 = D
0 1 2 3 4 5 6 7 8 9
6
Programmable Logic Array (PLA)
• Compared to a ROM and a PAL, a PLA is the most flexible having a
programmable set of ANDs combined with a programmable set of
ORs.
• Advantages
– A PLA can have large N and M permitting implementation of equations
that are impractical for a ROM (because of the number of inputs, N,
required
– A PLA has all of its product terms connectable to all outputs, overcoming
the problem of the limited inputs to the PAL ORs
– Some PLAs have outputs that can be complemented, adding POS
functions
• Disadvantage
– Often, the product term count limits the application of a PLA. Two-level
multiple-output optimization reduces the number of product terms in an
implementation, helping to fit it into a PLA.
7
Programmable Logic Array Example
A
 What are the equations for F1 and F2?
B  Could the PLA implement the
functions without the XOR gates?
C
X X 1 X X AB
X X 2 X BC X Fuse intact
Fuse blown
X X 3 X AC
X X 4 X AB
X 0
C C B B AA
X 1
F1
• 3-input, 3-output PLA with 4
product terms F2
8
Combinational Functions and
Circuits
• Rudimentary logic functions
• Decoding
• Encoding
• Selecting
9
Rudimentary Logic Functions
TABLE 4-1
• Functions of a single Functions ofOne Variable
variable X
X F=0 F=XF= X F=1
• Can be used on the
inputs to functional 0 0 0 1 1
blocks to implement 1 0 1 0 1
other than the block’s
V CC or V DD
intended function
1 F= 1 F= 1 X F= X
(c)
0 F= 0 F= 0
X F= X
(a) (b) (d)
10
Multiple-bit Rudimentary Functions
• Multi-bit Examples:
A F3 A
3 2
1 F2 1 2 4 4 2:1 F(2:1)
F F
0 F1 0 1
0 (c)
A F0 A
(a) (b) 3
4 3,1:0 F(3), F(1:0)
F
(d)
• A wide line is used to represent a bus which is a vector signal
• In (b) of the example, F = (F3, F2, F1, F0) is a bus.
• The bus can be split into individual bits as shown in (b)
• Sets of bits can be split from the bus as shown in (c) for bits 2 and 1 of F.
• The sets of bits need not be continuous as shown in (d) for bits 3, 1, and 0
of F.
11
Enabling Function
• Enabling permits an input signal to pass through to an
output
• Disabling blocks an input signal from passing through to
an output, replacing it with a fixed value
• The value on the output when it is disable can be Hi-Z (as
for three-state buffers and transmission gates), 0 , or 1
X
• When disabled, 0 output F
EN
• When disabled, 1 output
(a)
X
F
EN
(b)
12
Decoders
• Multiple-input multiple-output logic circuit which
maps coded inputs to coded outputs
• n input bits can code upto 2n different output bits
• n-to-m decoder: maps n-bit input to m-bit output
where m < 2n
13
Decoders
• General decoder structure
• Typically n inputs, 2n outputs

– 2-to-4, 3-to-8, 4-to-16, etc.
14
Binary 2-to-4 decoder
Note “x” (don’t care) notation.
15
2-to-4-decoder logic diagram
m0=I1’I0’
m1=I1’I0
m2=I1I0’
m3=I1I0
16
Decoder Expansion
3-to-8 decoder out of 2 2-to-4 decoders with enable
17
Decoder and OR Gate Implementation of
a Binary Adder
• Arithmetic sum of three bits X,Y,Z
• Output pair (C,S)
S(X,Y,Z) =  m(1,2,4,7)
C(X,Y,Z) =  m(3,5,6,7)
18
S(X,Y,Z) =  m(1,2,4,7)
C(X,Y,Z) =  m(3,5,6,7)
19
Decoder Applications
• Microprocessor memory systems
– Selecting different banks of memory
• Microprocessor input/output systems
– Selecting different devices
• Microprocessor instruction decoding
– Enabling different functional units
• Memory chips
– Enabling different rows of memory depending on address
• Lots of other applications
– Seven segment decoder, 4-to-7 decoder
20
Encoders vs. Decoders
Decoder Encoder
21
Binary encoders
22
Need priority in most applications
23
Priority Encoder
24
A0 = D3 + D1D2’
A1 = D2 + D3
V = D0 + D1 + D2 + D3
25
Another approach to the design of
8-input priority encoder
26
Priority-encoder logic equations
27
Selecting
• Selecting of data or information is a critical
function in digital systems and computers
• Circuits that perform selecting have:
– A set of information inputs from which the selection is
made
– A single output
– A set of control lines for making the selection
• Logic circuits that perform selecting are called
multiplexers
• Selecting can also be done by three-state logic or
transmission gates
28
Multiplexers
• MUX:
– Selects binary information from one of many input
lines and directs the information to a single output line.
– Selection of a particular input is controlled by a set of
input variables.
– # of selection control bits: n
2 n-to-1 MUX
– # of possible input lines: 2n
– # of output: 1
29
Multiplexers
30
4-to-1-Line MUX
31
Quadruple 2-to-1-Line MUX
32
Combinational Circuit Implementation
Using MUX
F(X,Y,Z)=m(1,2,6,7) using a 4-to-1 MUX
33
F(A,B,C,D)=m(1,3,4,11,12,13,14,15)
34
Demultiplexer
• Inverse of the MUX

• Receives information from
a single line and transmits
it to one of the 2n possible
output lines
• 1-to-4-Line DMUX /
2-to-4-Line Decoder
35
Binary Adders
• Arithmetic circuits:
– combinational circuits with add, subt, mult & div.
• Present a hierarchical design
– Simple addition of two bits
• 0+0 = 02, 0+1 = 12, 1+0 = 12 and 1+1 = 102
– Half Adder:
• Combinational circuit that adds two bits
– Full Adder:
• Combinational circuit that adds three bits (two input, one
carry)
36
Half Adder
• Sum of two binary digits
S=X’Y+XY’
C=XY
37
Full Adder
• Sum of three binary digits
38
Logic Diagram for Full Adder
XY Z
XY Z(XY)
XY + Z(XY)
39
Binary Ripple Carry Adder
• The parallel adder of n binary full adders

• Carry out  Carry in of next full adder
40
Carry Lookahead Adder
• Ripple carry adder

– Simple but has a long
circuit delay
• Define a partial full
adder
• Try to lower gate delays
for ripple carry adder
41
Binary Adder/Subtractor
42
Overflow
• When does it occur? 01110 10000

• How do we detect it? +5 0101 -4 1100
+7 0111 -6 1010
+12 ? 01100 -10 ? 10110
43
Binary Multipliers
44
4-bit by 3-bit multiplier
45

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Programmable Configurations

• Read Only Memory (ROM) –

(a) Programmable read-only memory (PROM)

Programmable Programmable Fixed

(b) Programmable array logic (PAL) device

Programmable Programmable Programmable Programmable

(c) Programmable logic array (PLA) device

(a) (b) (d)

• Typically n inputs, 2n outputs

Note “x” (don’t care) notation.

• Inverse of the MUX

• Sum of two binary digits

• Sum of three binary digits

• The parallel adder of n binary full adders

• Ripple carry adder

• When does it occur? 01110 10000

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