A

Project Review Seminar

on
DESIGNE AND IMPLIMENTATION OF APPLICATION
SPECIFIC LOW POWER MULTIPLIERS
BACHELOR OF TECHNOLOGY
In
ELECTRONICS AND COMMUNICATION ENGINEERING
By
K SAI KISHORE -13WJ1A04J8
K RAMA RAO -13WJ1A04L3
J NAVVENKUMAR-14WJ5A0418
Under the Guidance of
M SWETHA

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

GURU NANAK INSTITUIONS TECHNICAL CAMPUS
School of Engineering and Technology 1
2016-17
 Outline
Objective
ABSTRACT
Problem Definition
Problem Approach
Block Diagram – Explanation
Schematic Diagram
Algorithm or Flow Chart – Explanation
Results & discussion
Conclusions
Future Scope
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 Objective
• The multipliers proposed are target
application domains where the input data
have specific characteristics
• replace the multiplier with a minimum
number of additions and shifts in order to
decrease power dissipation
• . The proposed architectures reduce power by
exploiting the statistics of the input data.
Benefits are achieved for specific applications
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• Increased circuit complexity means more
static power dissipation and may increase the
overall power needs

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 ABSTRACT
• The multipliers are mainly focusing for low power.
• Here proposed two architectures for two inputs signed
multipliers namely selective activation multiplier and
partitioned multiplier.
• The proposed technique is mainly applied in DCT and DWT
Application.
• Power is reduced. The proposed multiplier is applied to all low
power techniques with moderate area and time overhead.

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 Problem Definition
• present a multiplier architecture which utilizes
the dynamic operand interchange technique.
• That technique has more no of partitioned
multipliers and uses more power

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 Problem Approach

• To reduce number of partial products we use

some vedic mathematic technique called
"urdva triyanka sutram” to reduce partial
products
• By that technique we designed an
architectures namely partitioned
multiplication and selective activation

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 Block Diagram – Explanation

• Partitioned multiplier architecture

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• the multiplication is divided into four
independent multiplications which compute
four products p22, p21, p12, and p11
• the architecture provides two paths, one for
small-number and one for large-number
multiplications
• Then the urdva triyanka sutram executes

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Algorithm(urdva triyanka srutram)
• In English it is called as Vertically and
Crosswise

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• Process: (Left –> Right)
• Vertical Multiplication of 1st digits of the
numbers.
• Crosswise Multiplication Addition (i.e.
Crosswise Multiplication and adding them).
• Vertical Multiplication of last digits of the
numbers.

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• For all steps, except 1st step, each step
(compartment) needs to have ONLY 1 digits. If
not then carry forward initial digits to previous
compartment (Check below examples to
understand).

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• For 3 digits

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 Results
• Extensive power consumption simulations
show that by taking advantage of the
characteristics of the input data and the
processing algorithm
• architectures reduce power consumption

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 Future Scope
• The proposed architectures can be combined
with other techniques in both the internal
architecture and the algorithmic level to
further reduce power consumption

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• What is the difference between block diagram
& Schematic Diagram?
• Add date..

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