THE INVERTERS

Engr. Ronald Bolor Baral, ECE, ECT

DIGITAL GATES
Fundamental Parameters

• Functionality
• Reliability, Robustness
• Area
• Performance
• Speed (delay)
• Power Consumption
• Energy
Noise in Digital Integrated Circuits

VDD
v(t)
i(t)

(a) Inductive coupling (b) Capacitive coupling (c) Power and ground
noise
DC Operation:
Voltage Transfer Characteristic

V(y)
V(x) V(y)

V f
OH
V(y)=V(x)

V Switching Threshold
M

VOL

VOL V V(x)
OH

Nominal Voltage Levels

Mapping between analog and digital signals

V V(y)
"1" OH
Slope = -1
V V
IH OH

Undefined
Region
Slope = -1
V
IL VOL
"0"
V
OL V V V(x)
IL IH
Definition of Noise Margins

"1"
V
OH
NMH
V
Noise Margin High IH
Undefined
Region
Noise Margin Low
NML V
IL
V
OL
"0"

Gate Output Gate Input

The Regenerative Property

...
v0 v1 v2 v3 v4 v5 v6

(a) A chain of inverters.

v1, v3, ... v1, v3, ...

f(v) finv(v)

finv(v) f(v)

v0, v2, ... v0, v2, ...

(b) Regenerative gate (c) Non-regenerative gate
Fan-in and Fan-out

(a) Fan-out N

M
(b) Fan-in M
N
The Ideal Gate

Vout

Ri = 

Ro = 0
g= 

Vin
VTC of Real Inverter

5.0

4.0 NML

3.0
Vout (V)

2.0
VM
NMH
1.0

0.0 1.0 2.0 3.0 4.0 5.0

Vin (V)
Delay Definitions

Vin

50%

t
t t
pHL pLH
Vout
90%

50%

10% t
tf tr
Ring Oscillator

v0 v1 v2 v3 v4 v5

v0 v1 v5

T = 2  tp N
Power Dissipation
CMOS INVERTER
The CMOS Inverter:
A First Glance
VDD

Vin Vout

CL
CMOS Inverters

VDD

PMOS

1.2mm
=2l
Out
In
Metal1

Polysilicon

NMOS
GND
Switch Model of CMOS Transistor

|V GS|

Ron

|VGS| > |VT|

|VGS| < |VT|
CMOS Inverter: Steady State Response

VDD VDD

Ron
VOH = VDD
Vout
Vout VOL= 0

Ron VM = f(Ronn,Ronp)

Vin = V DD Vin = 0
CMOS Inverter: Transient Response

VDD

tpHL = f(Ron.CL)
= 0.69 RonCL

Vout
Vout ln(0.5)
CL
1 VDD
Ron

0.5
0.36

Vin = V DD
t
RonCL
CMOS Properties

• Full rail-to-rail swing

• Symmetrical VTC
• Propagation delay function of load capacitance and
resistance of transistors
• No static power dissipation
• Direct path current during switching
Voltage Transfer
Characteristic
PMOS Load Lines

IDn
V in = V DD -VGSp
IDn = - IDp
V out = VDD -VDSp

V out

IDp IDn IDn

Vin=0 Vin=0

Vin=3 Vin=3

V DSp V DSp Vout

VGSp=-2

VGSp=-5
Vin = V DD-VGSp Vout = V DD-VDSp
IDn = - IDp
CMOS Inverter Load Characteristics

In,p
V in = 0 Vin = 5

NMOS
PMOS

Vin = 4 Vin = 1 Vin = 4

Vin = 3 Vin = 2 Vin = 3 Vin = 2

Vin = 4 Vin = 2 Vin = 1

V in = 3
Vin = 5 Vin = 0
CMOS Inverter VTC

Vou t NMOS off

PMOS lin

5 NMOS sat
PMOS lin
4

NMOS sat
3

PMOS sat
2

NMOS lin
PMOS sat NMOS lin
1

PMOS off

1 2 3 4 5 Vin
Simulated VTC

4.0
Vout (V)

2.0

0.0
0.0 1.0 2.0 3.0 4.0 5.0
Vin (V)
Gate Switching Threshold

4.0

3.0
VM

2.0

1.00.1 0.3 1.0 3.2 10.0

kp/kn
MOS Transistor Small Signal Model

G D
+
vgs gmvgs ro
-

S
Determining VIH and VIL
Propagation Delay
CMOS Inverter: Transient Response

VDD

tpHL = f(Ron.CL)
= 0.69 RonCL

Vout
Vout ln(0.5)
CL
1 VDD
Ron

0.5
0.36

Vin = V DD
t
RonCL
CMOS Inverter Propagation Delay

VDD

tpHL = CL Vswing/2
Iav

Vout CL
~
Iav CL kn VDD

Vin = V DD
Computing the Capacitances

VDD VDD

M2
Cdb2 Cg4 M4
Cgd12
Vin Vout Vout2

Cdb1 Cw Cg3
M1 M3
Interconnect

Fanout
Vin Vout
Simplified
Model CL
CMOS Inverters

VDD

PMOS

1.2mm
=2l
Out
In
Metal1

Polysilicon

NMOS
GND
The Miller Effect

Cgd1 Vout
V
V Vout

V
Vin 2Cgd1

M1
M1 V
Vin

“A capacitor experiencing identical but opposite voltage swings

at both its terminals can be replaced by a capacitor to ground,
whose value is two times the original value.”
Computing the Capacitances
Impact of Rise Time on Delay

0.35

0.3
tpHL(nsec)

0.25

0.2

0.15
0 0.2 0.4 0.6 0.8 1
trise (nsec)
Delay as a function of VDD

28

24

20
Normalized Delay

16

12

0
1.00 2.00 3.00 4.00 5.00
VDD (V)
Where Does Power Go in CMOS?

• Dynamic Power Consumption

Charging and Discharging Capacitors

• Short Circuit Currents

Short Circuit Path between Supply Rails during Switching

• Leakage
Leaking diodes and transistors
Dynamic Power Dissipation
Vdd

Vin Vout

CL

Energy/transition = CL * Vdd2

Power = Energy/transition * f = CL * Vdd2 * f

Not a function of transistor sizes!

Need to reduce CL, Vdd, and f to reduce power.
 Impact of
Technology Scaling
Technology Evolution
Technology Scaling (1)

Minimum Feature Size

Technology Scaling (2)

Number of components per chip

Propagation Delay Scaling
Technology Scaling Models

• Full Scaling (Constant Electrical Field)

ideal model — dimensions and voltage scale
together by the same factor S

• Fixed Voltage Scaling

most common model until recently —
only dimensions scale, voltages remain constant

• General Scaling
most realistic for todays situation —
voltages and dimensions scale with different factors
Scaling Relationships for Long Channel
Devices
Scaling of Short Channel Devices