K.

JASHWANTH REDDY(UR15EC002)
K.D.SAI PAVAN(UR15EC007)
YV.KEERTHI KANTH(UR15EC226)
G.DIWAKAR REDDY(UR15EC241)

GUIDE: DR. D. JACKULINE MONI

PROFESSOR, ECE-DEPARTMENT
OBJECTIVE
• To design a p-channel LDMOS transistor in 180nm-Technology for
RF application.
• To optimize the device for better Ion/Ioff ratio.
• To study the DC characteristics of the device.
PARAMETER SPECIFICATIONS
 Mask name= P-WELL left=4 right=8
 Mask name= POLY left= 2.5 right= 5.45 negative
 Mask name= PBODY left= 0.0 right=0.5
 Mask name = STI left=4.2 right=6.7 negative
 Mask name= PPLUS segments= “ 0.5 2.5 6.7 8.0”
 Mask name= CONTACTS segments= “ 0.0 0.25 2.25 2.0 6.7 8.0”
 Oxide thickness= 0.075 um
 Silicon thickness= 0.3 um
 Boron concentration= 1e15<cm-3>
 Phosphorus concentration= 4e13<cm-3>
POWER MOSFETS
 DMOS- Double-Diffused MOS
 The device is widely used in switching applications requiring high voltage and
high frequency behavior.
 VMOS- Vertical MOS
 The device has V-shaped gate region. The devices are used for applications
requiring medium powers such as power amplifiers and switching.
 LDMOS- Laterally Diffused MOS
 LDMOS is an asymmetric power MOSFET device. It is designed for
applications requiring lower on-resistance and higher blocking voltage.
 The device is fabricated using diffusion and ion implantation processes.
 Major development has been with focus on parameters important for mobile
communications, such as gain, efficiency, linearity, increased operation
frequency.
P-CHANNEL LDMOS DEVICE
DEVICE CREATION FLOWCHART
SUBSTRATE DEFINITON

P-WELL (DRAIN TO GATE)

SHALLOW TRENCH
ISOLATION(STI)

POLY SILICON GATE

FORMATION
Ctd.,

P-WELL (GATE TO SOURCE)

SPACERS(SOURCE/GATE/
DRAIN)

N-WELL(BODY CONTACT)

CONTACT FORMATION
DEVICE CREATION
EXPLANATION
SUBSTRATE CREATION:
• The simulation is initialized with a block of boron-doped n- type silicon
substrate. The initial concentration of the substrate is set using the
@psubD@ Sentaurus Workbench input parameter.
• P-WELL ( DRAIN TO GATE):
• An p-type well is created in the initial p-substrate. The n- well region is
defined using the PWELL mask layer and region is created from drain to
gate.
• A high- energy implantation of phosphorus is performed with an
implantation energy and dose of 300 keV and @pwellD@, respectively.
After the implantation process, a thermal annealing process is initiated.
SHALLOW TRENCH ISOLATION (STI):
 After creation of the p-well region, the shallow trench in the extended drain
region of the device is created.
POLY SILICON GATE FORMATION:
 Gate oxide is deposited and a single-step diffusion process is initiated.
 Polysilicon material is deposited after the diffusion process step using
the deposit command with the POLY mask layer.
P-WELL (GATE TO SOURCE):
 A p-well region with the mask layer is created from the gate terminal
to source terminal
SPACERS (SOURCE/GATE/DRAIN):
 A spacer is created by depostion and etching of oxide layer
with the given thickness .
 First create the spacer for source and gate terminals then
create another spacer for gate and drain .
N-WELL (BODY CONTACT):
 An n-well is created in the initial p-substrate. The n-well region is
defined using the NWELL mask layer.
 A high- energy implantation of phosphorus is performed with an
implantation energy and dose of 300 keV and @nwellD@,
respectively. After the implantation process, a thermal annealing
process is initiated.
CONTACT FORMATION:
 Electrical contacts to perform device characterization are defined.For
the electrical characteristics simulation, a separate mesh is needed
according to the device simulation requirements.
 A finer mesh is placed in the areas where the electric field and the
doping density change rapidly, such as trench corners, material
interfaces, and p-n junctions.
DEVICE SIMULATION
 This section presents the device
simulation details related to the
Id–Vg, Id–Vd and breakdown
voltage characteristics of the
LDMOS device.
 Id-vg graph:
 Vg=10 as constant and varying
Vds as -10.
Id-Vd graph:

• Vd=-10
CONCLUSION:
 Process and device simulations of an p-type LDMOS device have
been performed using the TCAD Sentaurus tool suite.
 DC device simulations have been performed to extract the circuit
design parameters.
STATUS:
Work completed:
• Device created with given dimensions.
• Id-Vg and Id-Vd characteristics are obtained.
Work to be done:
• Trap analysis of the device.
• Conference presentation.
 REFERENCE
J. F. Chen et al., “Convergence of Hot-Carrier-Induced Saturation Region Drain
Current and On-Resistance Degradation in Drain Extended MOS Transistors,”
IEEE Transactions on Electron Devices, vol. 56, no. 11, pp. 2843–2847, 2009.
J. F. Chen et al., “On-Resistance Degradation Induced by Hot-Carrier Injection
in LDMOS Transistors With STI in the Drift Region,” IEEE Electron Device
Letters, vol. 29, no. 9, pp. 1071–1073, 2008.
 O.Penzin et al., “MOSFET Degradation Kinetics and Its Simulation,” IEEE
Transactions on Electron Devices, vol. 50, no. 6, pp. 1445–1450, 2003.
 Orouji, A.A., Pak, A.: A novel technique for electric field control to improve
breakdown voltage. Mater. Sci. Semicond. Process. 34, 230–235 (2015).
 Pak, A., Orouji, A.A.: A novel laminated gate to improve the ON-state
resistance of LDMOS transistors. J. Comput. Electron. 15, 1071–1076 (2016).
 Xia, C., Cheng, X., Wang, Z., Xu, D., Cao, D., Zheng, L., Shen, L., Yu, Y.,
Shen, D.: Improvement of SOI trench LDMOS performance with double
vertical metal field plate. IEEE Trans. Electron. Devices61(10), 3477–3482
(2014).
ctd.,
 Pak, A., Orouji, A.A.: A novel laminated gate to improve the ON-state
resistance of LDMOS transistors. J. Comput. Electron. 15, 1071–
1076 (2016).
 Xia, C., Cheng, X., Wang, Z., Xu, D., Cao, D., Zheng, L., Shen, L.,
Yu, Y., Shen, D.: Improvement of SOI trench LDMOS performance
with double vertical metal field plate. IEEE Trans. Electron.
Devices61(10), 3477–3482 (2014)
 Y. Wimmer et al., "Physical modeling of hot-carrier degradation in
nLDMOS transistors", Proc. IEEE Int. Integr. Rel. Workshop Final
Rep. (IIRW), pp. 58-62, Oct. 2014.