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POWER-EFFICIENT RAM MAPPING

ALGORITHM FOR FPGA EMBEDDED
MEMORY BLOCKS

PRESENTING BY:

SHERIN SCARIA
SEMESTER 1.M.Tech
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INTRODUCTION

• Embedded memory blocks have been found to consume

between 10% and 20% of core dynamic power in typical
FPGA designs
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INTRODUCTION
• The application domain of FPGAs is expanding
to include mobile and power-sensitive
environments
• In FPGA, embedded memory blocks are
implemented using synchronous SRAM.
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INTERNAL BEHAVIOUR OF SYNCHRONOUS

RAM

• SRAM contains R/W enable signals, clock enable

signals
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INTERNAL BEHAVIOUR OF
SYNCHRONOUS RAM

READ OPERATION :
The following events occur in sequence, in response to a rising
clock edge.
oThe memory port clock (MClk) is strobed, causing the BIT
lines to be precharged to Vcc.
oThe read address is decoded, and one word line is activated.
oThe BIT line difference is identified by sense amplifiers,
causing the read data to be strobed into a column multiplexer.
oThe Read Data passes through the column multiplexer and a
latch conditioned by Read Enable to the RAM external Read
Data lines.
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INTERNAL BEHAVIOUR OF
SYNCHRONOUS RAM

WRITE OPERATION :
o MClk is strobed, causing the BIT lines to be
precharged to Vcc.
oThe Write Enable signal, which conditioned by
MClk,creates a write pulse that transfers write
data to the write buffers, and a word line is
activated following write address decode.
o The write buffer data is stored in the RAM
cell.
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INTERNAL BEHAVIOUR OF
SYNCHRONOUS RAM
• In R/W operations mainly dynamic power is
consumed by BIT line precharging.
• To eliminate the precharging we are using a clock
enable signal, there by reducing power
consumption.
• The goal of power aware RAM mapping is to
reduce memory precharges.
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TYPICAL RAM MAPPING FLOW

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TYPICAL RAM MAPPING FLOW

1) Logical memory creation. User-defined RAM descriptions
are processed by the FPGA compilation software to create logical
memories with the desired characteristics.

2) Logical-to-physical RAM processing. Logical RAMs are

converted into one or more RAM blocks, which match the external
interface and size constraints of available embedded memory
blocks.

3) Embedded memory block placement. RAM blocks and

associated control logic are assigned to available on-chip
embedded memory block and logic resources.
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REASONS FOR DYNAMIC POWER

CONSUMPTION
• In the case of asynchronous memories, read and
write enable signals were used, instead of clock
enable signals.
• Size of logical memory may not match with that
of the embedded blocks.
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SOLUTION : EFFECTIVE RAM

MAPPING
Two algorithms
1)Conversion of read and write enables to
read and write clock enable signals.
2) Implement a multi banked RAM
mapping for mapping to more than one
embedded memory blocks.
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CONVERSION OF ENABLE SIGNALS

Read clock enable
• Both read enable and read clock enable signals
must be active to successfully perform an
embedded memory block read transaction.
• Read enable input is attached to a control signal
and read clock enable input is always tied to
active logic 1.
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MULTI-BANKED RAM MAPPING

• Done by variation in depth and width

configuration.

• There are 2 types of banking.

1) Vertical slicing.
2) Horizontal slicing.
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VERTICAL SLICING
• The memory is sliced along the depth.
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VERTICAL SLICING
• Advantage:
▫ No much address decoders and multiplexers, So
power consumption by these blocks is nil.

• Disadvantage:
▫ Each memory block is active in each memory
access, so substantial power consumption.
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HORIZONTAL SLICING
• Memory is divided along its width.
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HORIZONTAL SLICING
• Advantage:
▫ Only one memory block is active in each memory
access, so no substantial power consumption.

• Disadvantage:
▫ Dynamic power is consumed by added address
decoder and multiplexer.
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SO WHICH SLICING TECHNIQUE..?

• In Vertical slicing implementation, memory
block power is increased and multiplexer,
decoder power is decreased.
• In Horizontal slicing implementation,
multiplexer, decoder power is increased and
memory block power is decreased.
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LOGICAL RAM PARTITIONING

ALGORITHM
• To evaluate the relative power consumption of a
series of logical to physical ram mapping.

• Mapping is based on no. of embedded memory

blocks, decoder, multiplexer etc.

• Mapping evaluation is performed for each block

sizes.
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LOGICAL RAM PARTITIONING

ALGORITHM
• The relative cost for each mapping is determined by equation

 Cost=W*Pmux+N*Pram+Paddr_decoder

Cost - relative power cost for the mapping

W - width of the logical RAM
Pmux – per bit dynamic power of a read port multiplexer
N –number of required embedded memory blocks
Pram – per block dynamic power
Paddr_decode –dynamic power consumption of the address
decoder.
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POWER-AWARE MEMORY PARTITIONING

ALGORITHM

1.Initially resource-feasible mapping for each logical

memory block is determined.
2.All possible logical-to-physical mapping are counted
and evaluated based on their power consumption.
3. For each logical memory, the minimum power depth
and width configuration of each memory block is
stored.
4.Then initial physical mapping is replaced by low
power mapping.
5.It is again re-ordered so that mapping having lowest
dynamic power is considered first.
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CONCLUSION
• These techniques take advantage of the internal
structure of FPGA embedded memory to reduce
memory dynamic power dissipation.
• Embedded memory block clock enables are used
to deactivate RAM block pre-charging.
• Several optimizations for power-saving
approaches could be implemented in the future.
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REFERENCES
• R. Tessier, V. Betz, D. Neto, and T. Gopalsamy, “Power-aware RAM
mapping for FPGA embedded memory blocks,” in Proc.
ACM/SIGDA Int. Symp. Field Programmable Gate Arrays,
Monterey, CA, Feb. 2006,

• A. Ferrahi, G. Tellez, and M. Sarrafzadeh, “Memory segmentation to

exploit sleep mode operation,” in Proc. ACM/IEEE Des. Autom.
Conf.,San Francisco, CA, Jun. 2003.

• H. Schmit and D. Thomas, “Address generation for memories

containingmultiple arrays,” IEEE Trans. Very Large Scale Integr.
(VLSI) Syst.,vol. 17, no. 5, pp. 377–385, May 2002.
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THANK YOU