Chapter: Memory Management

Hardware Support: for Page Table

Implementation
 Each operating system has its own methods for storing page tables.

Some allocate a page table for each process. A pointer to the page
table is stored with the other register values (like the instruction
counter) in the process control block.

When the dispatcher is told to start a process, it must reload the

user registers and define the correct hardware page-table values from
the stored user page table.
Hardware Support: for Page Table
Implementation
Each operating system has its own methods for storing
page tables.
– Some allocate page table for each process
– Pointer to page table is stored with other register values (e.g.
instruction pointer) in PCB.
– When dispatcher starts a process, It:
• Reload user register
• Define correct hardware page table value from stored user table

Page lookups must be done for every memory reference,

and whenever a process gets swapped in or out of the
CPU, its page table must be swapped, along with the
instruction registers.
Hardware Support: for Page Table
Implementation
Hardware implementation of page table: Methods:
1. Use Registers
– One option is to use a set of registers for the page
table
– The use of registers for the page table is satisfactory if
the page table is reasonably small (for example, 256
entries).
– Most contemporary computers, however, allow the page
table to be very large (for example, 1 million entries).
– The use of fast registers to implement the page table is
not feasible.
Hardware Support: for Page Table
Implementation
2. An alternate option is to:

– Store the page table in main memory, and to use a

single register ( called the page-table base register,
PTBR ) to record where in memory the page table is
located.
– Process switching is fast, because only the single
register needs to be changed.
– The address of a page table in memory is pointed by:
page table base register
Hardware Support: for Page Table
Implementation
The problem with this approach is the time required to
access a user memory location.
 If we want to access location i, we must first index into
the page table, using the value in the PTBR offset by the page
number for i.
This task requires a memory access. It provides us with the
frame number, which is combined with the page offset to
produce the actual address.

Two memory accesses

are needed to access a byte (one for the page-table entry, one
for the byte). Thus, memory access is slowed by a factor of 2.
Hardware Support: for Page Table
Implementation
– Solution to two memory accesses:
– Use a very special high-speed memory device called
the translation look-aside buffer, TLB.
– Each entry in the TLB consists of two parts:
– a key (or tag) and a value.
– When the associative memory is presented with an item, the
item is compared with all keys simultaneously.
– If the item is found, the corresponding value field is returned.
– The benefit of the TLB is that it can search an entire table for
a key value in parallel, and if it is found anywhere in the table,
then the corresponding lookup value is returned.
Hardware Support: for Page Table
Implementation

– TLB is not large enough to hold the entire page table.

– So used as a cache device.
– The percentage of time that the desired information is found
in the TLB is termed the hit ratio.
– The percentage of time that the desired information is not
found in the TLB is termed the miss ratio.
Paging hardware with TLB
Example

– 40% slowdown to get the frame

Effective access time = hit ratio x time taken for TLB hit +
miss ratio x time taken for TLB miss
Example

Explanation:
- TLB hit takes 120 nanoseconds total ( 20 to find the
frame number and then another 100 to go get the data )
- TLB miss takes 220 ( 20 to search the TLB, 100 to go
get the frame number, and then another 100 to go get
the data.

- Effective access time = hit ratio x time taken for TLB

hit + miss ratio x time taken for TLB miss
Problem
Memory Protection
• It is accomplished by Protection Bits associated with each frame
→ Valid – Invalid Bit
• These bits are kept in page table
• Every reference to the memory goes through page table and finds
correct frame number.
• When bit is set to valid: indicates that associated page is in
process's logical address space and is valid page.
• When bit is set to invalid: indicates that associated page is not
in process's logical address space and is invalid page.
Memory Protection
Structure of the Page Table
common techniques for structuring the page table: hierarchical paging, hashed
page tables, and inverted page tables

1. Hierarchical Paging (also known as a forward-mapped page table)

If logical address space is huge i.e.(2^32 to 2^64).
In such an environment, the page table itself becomes excessively
large.
page table may consist of up to 1 million entries
One simple solution to this problem is to divide the page table
into smaller pieces.

One way is to use a two-level paging algorithm, in which the page

table itself is also paged
Structure of the Page Table
Consider the system with a 32-bit logical address space and a page size of 4
KB.
A logical address is divided into a page number consisting of 20 bits and a
page offset consisting of 12 bits.

Because we page the page table, the page number is further divided into a
10-bit page number and a 10-bit page offset. Thus, a logical address is as
follows:

where p1 is an index into the outer page table and p2 is the displacement
within the page of the inner page table.
Because address translation works from the outer page table inward, this
scheme is also known as a forward-mapped page table.
Address translation
Structure of the Page Table
Structure of the Page Table
2. Hashed Page tables

A common approach for handling address spaces larger than 32 bits is

to use a hashed page table, with the hash value being the virtual
page number.
Each entry in the hash table contains a linked list of elements that
hash to the same location.

Each element consists of three fields: (1) the virtual page number, (2)
the value of the mapped page frame (3) a pointer to the next element
in the linked list.
Structure of the Page Table
2. Hashed Page tables

How it works:

1. The virtual page number in the virtual address is hashed into

the hash table.
2. The virtual page number is compared with field 1 in the first
element in the linked list.
3. If there is a match, the corresponding page frame (field 2) is
used to form the desired physical address.
4. If there is no match, subsequent entries in the linked list are
searched for a matching virtual page number.
Structure of the Page Table: Hashed Page Table
Structure of the Page Table
3. Inverted Page Table

Inverted page table is a global page table maintained by the

operating system for all the processes. There is just one page table in
the entire system, implying that additional information needs to be
stored in the page table to identify page table entries corresponding to
each process.

It stores one entry per physical frame, and is a linear array where the
contents at each location is <pid (process id), virtual page number>
and the index of each location is the physical frame address.
The formula will change now:

<pid (id), virtual page number (p)> = page-table[f]

Structure of the Page Table
3. Inverted Page Table

This straightaway implies that look-ups can no more happen on the

virtual page number. The entire table has to be searched entry-by-
entry to find a matching entry having the pid equal to "id" and virtual
page number equal to "p".

The index location corresponding to the match is the physical frame

address (f), which then combined with the offset(d) gives the physical
address.

Each page table may consist of millions of entries. These tables may
consume large amounts of physical memory just to keep track of how
other physical memory is being used.
Structure of the Page Table
3. Inverted Page Table

In an inverted page table, for each occupied physical memory

frame there is an associated virtual page.

It is inverted in the sense that we look at mapping starting from

a physical memory frame back to a virtual page though the
actual address translation starts with a virtual page all the way
to a physical memory frame just like a normal page table.
Structure of the Page Table
3. Inverted Page Table

The idea behind inverted page tables is to have a single page table on
the operating system level that is not tied to any specific process. It is
based on the observation that the CPU only references entries in those
pages that are already present in memory. The number of pages that
are present in physical memory frames are far less than the total
number of virtual pages that are on disk. Having a single table that
maps occupied memory frames to virtual pages consumes far less
space than having a page table for each process that is big enough to
fit all virtual pages.
Segmentation
• It is a memory management scheme in which the memory
allocated to the process is non contiguous
• Logical address space is divided into number of small blocks
called segments
• Segments are of variable sized.

A C compiler might create separate segments for the following:

1. The code
2. Global variables
3. The heap, from which memory is allocated
4. The stacks used by each thread
5. The standard C library
Segmentation
• Users view memory as a collection of variable size segments.
With no necessary ordering of these segments

• Segmentation is memory-management scheme that supports user

view of memory

• A program is a collection of segments. A segment is a logical unit

such as:
main program, function, object, local variables, global variables,
data structures : stack, symbol table, arrays
User’s View of a Program
Logical View of Segmentation

1
4
1
2

3 2
4
3

user space memory space

Segmentation Architecture
• Each segment has a name and its length.
• Logical address consists of a two tuple:
<segment-number, offset>,
• Segment table – maps physical addresses; each table entry has:
– base – contains the starting physical address where the
segments reside in memory
– limit – specifies the length of the segment
• Segment-table base register (STBR) points to the segment
table’s location in memory
• Segment-table length register (STLR) indicates number of
segments used by a program;
segment number s is legal if s < STLR
Address Translation: Segmentation Hardware
Problems
Q1.if Segment 2 is 400 bytes long and begins at location 4300,
then a reference to byte 53 of segment 2 is mapped onto
location?
Ans: base address: 4300
Limit: 400
53<400 (I.e limit)
4300+53=4353.
Problems

Q2. A reference to byte 852 of segment 3 is mapped to?

Ans: 3200+852=4052.

Q3. A reference to byte 1222 of segment 0 is mapped to?

Ans: would result in a trap to OS, as this segment is only 1000
bytes long.
MCQ
1. Which one of the following is the address generated by
CPU?
a) physical address
b) absolute address
c) logical address
d) none of the mentioned
MCQ

c) logical address
MCQ
2. Memory management technique in which system stores and
retrieves data from secondary storage for use in main
memory is called
a) fragmentation
b) paging
c) mapping
d) none of the mentioned
MCQ
2.
b) paging
MCQ
3. The address of a page table in memory is pointed by
a) stack pointer
b) page table base register
c) page register
d) program counter
MCQ
3.
b) page table base register
MCQ
4. Program always deals with
a) logical address
b) absolute address
c) physical address
d) relative address
MCQ
4.
a) logical address
MCQ
5.
The page table contains
a) base address of each page in physical memory
b) page offset
c) page size
d) none of the mentioned
MCQ
5.

a) base address of each page in physical memory

MCQ
6.
Operating System maintains the page table for
a) each process
b) each thread
c) each instruction
d) each address
MCQ
6.

a) each process
MCQ
7. Locality of reference implies that the page reference being made
by a process
a. will always be to the page used in the previous page reference.
b. will always be to the page used in the previous page reference.
c. will always be to one of the pages existing in memory.
d. will always lead to a page fault.
MCQ
Ans 7: b