MICRO-PROCESSORS 8085

D.ARUN KUMAR
Intel 8085 Architecture
 Features of MICROPROCESSOR
 It is a 8 bit microprocessor.
 It is manufactured with N-MOS technology.
 It has 16-bit address bus and hence can address up to 216 = 65536
bytes (64KB)
 memory locations through A0-A15.
 The first 8 lines of address bus and 8 lines of data bus are multiplexed
AD0 – AD7.
 Data bus is a group of 8 lines D0 – D7.
 It supports external interrupt request.
 A 16 bit program counter (PC)
 A 16 bit stack pointer (SP)
 Six 8-bit general purpose register arranged in pairs: BC, DE, HL.
 It requires a signal +5V power supply and operates at 3.2 MHZ single
phase clock.
 It is enclosed with 40 pins DIP (Dual in line package).
 MEMORY

Program, data and stack memories occupy the same memory space. The total
addressable memory size is 64 KB.
Program memory - program can be located anywhere in memory. Jump, branch
and call instructions use 16-bit addresses, i.e. they can be used to jump/branch
anywhere within 64 KB. All jump/branch instructions use absolute addressing.
Data memory - the processor always uses 16-bit addresses so that data can be
placed anywhere.
Stack memory is limited only by the size of memory. Stack grows downward.
First 64 bytes in a zero memory page should be reserved for vectors used by RST
instructions.
 INTERRUPTS
 The processor has 5 interrupts. They are presented below in the order of their
priority (from lowest to highest):
 INTR is maskable 8080A compatible interrupt. When the interrupt occurs the
processor fetches from the bus one instruction, usually one of these
instructions:
 One of the 8 RST instructions (RST0 - RST7). The processor saves current
program counter into stack and branches to memory location N * 8
(where N is a 3-bit number from 0 to 7 supplied with the RST instruction).
 CALL instruction (3 byte instruction). The processor calls the subroutine,
address of which is specified in the second and third bytes of the instruction.
 RST5.5 is a maskable interrupt. When this interrupt is received the processor
saves the contents of the PC register into stack and branches to 2CH
(hexadecimal) address.
 INTERRUPTS Contd..,

 RST6.5 is a maskable interrupt. When this interrupt is received the processor

saves the contents of the PC register into stack and branches to 34H

(hexadecimal) address.
 RST7.5 is a maskable interrupt. When this interrupt is received the processor
saves the contents of the PC register into stack and branches to 3CH
(hexadecimal) address.
 TRAP is a non-maskable interrupt. When this interrupt is received the processor
saves the contents of the PC register into stack and branches to 24H
(hexadecimal) address.
 All maskable interrupts can be enabled or disabled using EI and DI instructions.
RST 5.5, RST6.5 and RST7.5 interrupts can be enabled or disabled individually
using SIM instruction.
RESET IN: When this signal goes low, the program counter (PC) is set to Zero,
μp is reset and resets the interrupt enable and HLDA flip-flops.

The data and address buses and the control lines are 3-stated during RESET and
because of asynchronous nature of RESET, the processor internal registers and
flags may be altered by RESET with unpredictable results.

RESET IN is a Schmitt-triggered input, allowing connection to an R-C network

for power-on RESET delay.Upon power-up, RESET IN must remain low for at
least 10 ms after minimum Vcc has been reached.

For proper reset operation after the power – up duration, RESET IN should be
kept low a minimum of three clock periods.

The CPU is held in the reset condition as long as RESET IN is applied. Typical
Power-on RESET RC values R1 = 75KΩ, C1 = 1μF.

RESET OUT: This signal indicates that μp is being reset. This signal can be used
to reset other devices. The signal is synchronized to the processor clock and lasts
an integral number of clock periods.
 Serial communication Signal
SID - Serial Input Data Line: The data on this line is loaded into accumulator bit
7 whenever a RIM instruction is executed.

SOD – Serial Output Data Line: The SIM instruction loads the value of bit 7 of
the accumulator into SOD latch if bit 6 (SOE) of the accumulator is 1.
DMA Signals

HOLD: Indicates that another master is requesting the use of the address and data
buses. The CPU, upon receiving the hold request, will relinquish the use of the
bus as soon as the completion of the current bus transfer.

Internal processing can continue. The processor can regain the bus only after the
HOLD is removed.

When the HOLD is acknowledged, the Address, Data RD, WR and IO/M lines are
3-stated.

HLDA: Hold Acknowledge: Indicates that the CPU has received the HOLD
request and that it will relinquish the bus in the next clock cycle.
 Serial communication Signal Contd..…

HLDA goes low after the Hold request is removed. The CPU takes the bus one
half-clock cycle after HLDA goes low.
READY This signal Synchronizes the fast CPU and the slow memory,
peripherals.
If READY is high during a read or write cycle, it indicates that the memory or
peripheral is ready to send or receive data.
If READY is low, the CPU will wait an integral number of clock cycle for
READY to go high before completing the read or write cycle.
READY must conform to specified setup and hold times.
 Registers

Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O and
load/store operations.
 Flag Register has five 1-bit flags.
 Sign - set if the most significant bit of the result is set.
 Zero - set if the result is zero.
 Auxiliary carry - set if there was a carry out from bit 3 to bit 4 of the result.
 Parity - set if the parity (the number of set bits in the result) is even.
 Carry - set if there was a carry during addition, or borrow during
subtraction/comparison/rotation.
 General Registers
 8-bit B and 8-bit C registers can be used as one 16-bit BC register pair. When
used as a pair the C register contains low-order byte. Some instructions may use
BC register as a data pointer.
 8-bit D and 8-bit E registers can be used as one 16-bit DE register pair. When
used as a pair the E register contains low-order byte. Some instructions may use
DE register as a data pointer.
 8-bit H and 8-bit L registers can be used as one 16-bit HL register pair. When
used as a pair the L register contains low-order byte. HL register usually contains
a data pointer used to reference memory addresses.
 Stack pointer is a 16 bit register. This register is always
decremented/incremented by 2 during push and pop.
 Program counter is a 16-bit register.
 Instruction Set of 8085
8085 instruction set consists of the following instructions:
• Data moving instructions.
• Arithmetic - add, subtract, increment and decrement.
• Logic - AND, OR, XOR and rotate.
• Control transfer - conditional, unconditional, call subroutine, return
from subroutine and restarts.
• Input/Output instructions.
• Other - setting/clearing flag bits, enabling/disabling interrupts, stack
operations,etc.
 DATA TRANSFER INSTRUCTIONS
MOV Copy from source to destination

MVI Move immediate 8-bit

LDA Load accumulator

LDAX Load accumulator indirect

LXI Load register pair immediate

LHLD Load H and L registers direct

STA Store accumulator direct

STAX Store accumulator indirect

SHLD Store H and L registers direct

XCHG Exchange H and L with D and E

SPHL Copy H and L registers to the stack pointer

XTHL Exchange H and L with top of stack

PUSH Push register pair onto stack

POP Pop of stack to register pair

OUT Output data from accumulator to a port with 8-bit address

IN Input data to accumulator from a port with 8-bit address

 ARITHMETIC INSTRUCTIONS
ADD Add register or memory to accumulator
ADC Add register to accumulator with carry
ADI Add immediate to accumulator
ACI Add immediate to accumulator with carry
DAD Add register pair to H and L registers
SUB Subtract register or memory from accumulator
SBB Subtract source and borrow from accumulator
SUI Subtract immediate from accumulator
SBI Subtract immediate from accumulator with borrow
INR Increment register or memory by 1
INX Increment register pair by 1
DCR Decrement register or memory by 1
DCX Decrement register pair by 1
DAA Decimal adjust accumulator
 CONTROL INSTRUCTIONS

NOP No operation
HLT Halt
DI Disable interrupts
EI Enable interrupts
RIM Read interrupt mask
SIM Set interrupt mask
 BRANCHING INSTRUCTIONS
JMP Jump unconditionally
JC Jump on carry
JNC Jump on no carry
JP Jump on positive
JM Jump on minus
JZ Jump on zero
JNZ Jump on no zero
JPE Jump on parity even
JPO Jump on parity odd
CALL Call unconditionally
CC Call on carry
CNC Call on no carry
CP Call on positive
CM Call on minus
CZ Call on zero
 LOGICAL INSTRUCTIONS
CMP Compare register or memory with accumulator
CPI Compare immediate with accumulator
ANA Logical AND register or memory with accumulator
ANI Logical AND immediate with accumulator
XRA Exclusive OR register or memory with accumulator
XRI Exclusive OR immediate with accumulator
ORA Logical OR register or memory with accumulator
ORI Logical OR immediate with accumulator
RLC Rotate accumulator left
RRC Rotate accumulator right
RAL Rotate accumulator left through carry
RAR Rotate accumulator right through carry
CMA Complement accumulator
CMC Complement carry
STC Set carry
 The 8085 Addressing Modes
For 8085, they are:
1. Immediate addressing.
2. Register addressing.
3. Direct addressing.
4. Indirect addressing.
Immediate addressing
Data is present in the instruction. Load the
immediate data to the destination provided.
Example: MVI R,data
Register addressing
Data is provided through the registers.
Example: MOV Rd, Rs
Direct addressing
Used to accept data from outside devices to
store in the accumulator or send the data stored
in the accumulator to the outside device. Accept
the data from the port 00H and store them into
the accumulator or Send the data from the
accumulator to the port 01H.
Example: IN 00H or OUT 01H
Indirect Addressing
This means that the Effective Address is
calculated by the processor. And the contents of
the address (and the one following) is used to
form a second address. The second address is
where the data is stored.
Note that this requires several memory accesses;
two accesses to retrieve the 16-bit address and
a further access (or accesses) to retrieve the
data which is to be loaded into the register.
 Instruction Set Classification
An instruction is a binary pattern designed inside a
microprocessor to perform a specific function. The
entire group of instructions, called the instruction set,
determines what functions the microprocessor can
perform.
These instructions can be classified into the following
five functional categories: data transfer (copy)
operations, arithmetic operations, logical operations,
branching operations, and machine-control operations.
 Data Transfer (Copy) Operations
This group of instructions copy data from a
location called a source to another location
called a destination, without modifying the
contents of the source.
 Arithmetic Operations
Addition - Any 8-bit number, or the contents of a register or
the contents of a memory location can be added to the
contents of the accumulator and the sum is stored in the
accumulator.
Subtraction - Any 8-bit number, or the contents of a register,
or the contents of a memory location can be subtracted from
the contents of the accumulator and the results stored in the
accumulator.
Increment/Decrement - The 8-bit contents of a register or a
memory location can be incremented or decrement by 1.
Similarly, the 16-bit contents of a register pair (such as BC)
can be incremented or decrement by 1. These increment and
decrement operations differ from addition and subtraction in
an important way; i.e., they can be performed in any one of
the registers or in a memory location.
 Logical Operations
AND, OR Exclusive-OR - Any 8-bit number, or the
contents of a register, or of a memory location can be
logically ANDed, Ored, or Exclusive-ORed with the
contents of the accumulator. The results are stored in the
accumulator.
Rotate- Each bit in the accumulator can be shifted either left
or right to the next position.
Compare- Any 8-bit number, or the contents of a register, or
a memory location can be compared for equality, greater
than, or less than, with the contents of the accumulator.
Complement - The contents of the accumulator can be
complemented. All 0s are replaced by 1s and all 1s are
replaced by 0s.
 Branching Operations
This group of instructions alters the sequence of program
execution either conditionally or unconditionally.
Jump - Conditional jumps are an important aspect of the
decision-making process in the programming. These
instructions test for a certain conditions (e.g., Zero or Carry
flag) and alter the program sequence when the condition is
met. In addition, the instruction set includes an instruction
called unconditional jump.
Call, Return, and Restart - These instructions change the
sequence of a program either by calling a subroutine or
returning from a subroutine. The conditional Call and
Return instructions also can test condition flags.
 Machine Control Operations
These instructions control machine functions such as
Halt, Interrupt, or do nothing.
The microprocessor operations related to data
manipulation can be summarized in four functions:
1.Copying data
2.Performing arithmetic operations
3.Performing logical operations
4.Testing for a given condition and alerting the
program sequence
 Important aspects of the instruction set
1.In data transfer, the contents of the source are not destroyed;
only the contents of the destination are changed. The data
copy instructions do not affect the flags.
2.Arithmetic and Logical operations are performed with the
contents of the accumulator, and the results are stored in the
accumulator (with some expectations). The flags are affected
according to the results.
3.Any register including the memory can be used for increment
and decrement.
4.A program sequence can be changed either conditionally or
by testing for a given data condition.
 Instruction Format
An instruction is a command to the microprocessor to perform a given
task on a specified data. Each instruction has two parts: one is task to
be performed, called the operation code (opcode), and the second is
the data to be operated on, called the operand. The operand (or data)
can be specified in various ways. It may include 8-bit (or 16-bit ) data,
an internal register, a memory location, or 8-bit (or 16-bit) address.
In some instructions, the operand is implicit.
Instruction word size
The 8085 instruction set is classified into the following three groups
according to word size:
1. One-word or 1-byte instructions
2. Two-word or 2-byte instructions
3. Three-word or 3-byte instructions
 One-Byte Instructions
A 1-byte instruction includes the opcode and operand in the same byte.
Operand(s) are internal register and are coded into the instruction. For
example:

These instructions are 1-byte instructions performing three different

tasks. In the first instruction, both operand registers are specified.
In the second instruction, the operand B is specified and the
accumulator is assumed. Similarly, in the third instruction, the
accumulator is assumed to be the implicit operand.
These instructions are stored in 8-bit binary format in memory;
each requires one memory location.
MOV rd, rs
rd <-- rs copies contents of rs into rd.
Coded as 01 ddd sss where ddd is a code for one of the 7 general
registers which is the destination of the data, sss is the code of
the source register.
Example: MOV A,B
Coded as 01111000 = 78H = 170 octal (octal was used
extensively in instruction design of such processors).
ADD r
A <-- A + r
 Two-Byte Instructions
In a two-byte instruction, the first byte specifies the operation code
and the second byte specifies the operand. Source operand is a data
byte immediately following the opcode. For example:

Assume that the data byte is 32H. The assembly language instruction is
written as
The instruction would require two memory locations to store in memory.
MVI r,data
r <-- data
Example: MVI A,30H coded as 3EH 30H as two contiguous bytes. This is
an
example of immediate addressing.
ADI data
A <-- A + data
OUT port
where port is an 8-bit device address. (Port) <-- A. Since the byte is not
the data but points directly to where it is located this is called direct
addressing
 Three-Byte Instructions
In a three-byte instruction, the first byte specifies the opcode,
and the following two bytes specify the 16-bit address. Note
that the second byte is the low-order address and the third byte
is the high-order address. opcode + data byte + data byte

For example:

This instruction would require three memory locations to store in

memory.
Three byte instructions - opcode + data byte + data byte
LXI rp, data16
rp is one of the pairs of registers BC, DE, HL used as 16-bit registers. The
two data bytes are 16-bit data in L H order of significance.
rp <-- data16
Example:
LXI H,0520H coded as 21H 20H 50H in three bytes. This is also
immediate addressing.
LDA addr
A <-- (addr) Addr is a 16-bit address in L H order. Example: LDA 2134H
coded as 3AH 34H 21H. This is also an example of direct addressing.
Add two 8-bit numbers
Statement: Add the contents of memory locations 4000H and 4001H and place the result
in memory location 4002H.
Source program
LXI H 4000H : HL points 4000H
MOV A, M : Get first operand
INX H : HL points 4001H
ADD M : Add second operand
INX H : HL points 4002H
MOV M, A : Store result at 4002H
HLT : Terminate program execution
Sample problem
(4000H) = 14H
(4001H) = 89H
Result     = 14H + 89H = 9DH
Subtract two 8-bit numbers
Statement: Subtract the contents of memory location 4001H from the memory location 2000H
and place the result in memory location 4002H.
Source program
LXI H, 4000H : HL points 4000H
MOV A, M : Get first operand
INX H : HL points 4001H
SUB M : Subtract second operand
INX H : HL points 4002H
MOV M, A : Store result at 4002H.
HLT : Terminate program execution
Sample problem:

(4000H) = 51H
(4001H) = 19H
Result = 51H - 19H = 38H
Finding one's complement of a number
Statement: Find the l's complement of the number stored at
memory location 4400H and store the complemented number
at memory location 4300H.
Source program:
LDA 4400B : Get the number
CMA : Complement number
STA 4300H : Store the result
HLT : Terminate
Sample problem:

(4400H) = 55H
Result = (4300B) = AAB
 PROGRAMMABLE PERIPHERAL
INTERFACE - INTEL 8255
Pins and Signals of 8255:
PIN DESCRIPTION - INTEL 8255    
Block diagram of 8255:
 Features of 8255
• The INTEL 8255 is a device used to parallel data transfer between
processor and slow peripheral devices like ADC, DAC, keyboard, 7-
segment display, LCD, etc.
• The 8255 has three ports: Port-A, Port-B and Port-C.
• Port-A can be programmed to work in any one of the three operating
modes mode-0, mode-1 and mode-2 as input or output port.
• Port-B can be programmed to work either in mode-0 or mode-1 as input or
output port. Port-C (8-pins) has different assignments depending on the
mode of port-A and port-B.
• If port-A and B are programmed in mode-0, then the port-C can perform
any one of the following functions.
• As 8-bit parallel port in mode-0 for input or output.
• As two numbers of 4-bit parallel ports in mode-0 for input or output.
• The individual pins of port-C can be set or reset for various control
applications.
 Features of 8255
• If port-A is programmed in mode- 1/mode-2 and port-B is
programmed in mode-1 then some of the pins of port-C are used
for handshake signals and the remaining pins can be used as input/
output lines or individually set/reset for control applications.
• The read/write control logic requires six control signals. These
signals are given below.
1. RD (low): This control signal enables the read operation. When
this signal is low, the microprocessor reads data from a selected
I/O port of the 8255A.
2. WR (low): This control signal enables the write operation. When
this signal goes low, the microprocessor writes into a selected I/O
port or the control register.
3. RESET: This is an active high signal. It clears the control register
and set all ports in the input mode.
 Features of 8255
4. CS (low), A0 and A1: These are device select
signals. They are,
Interfacing of 8255 with 8085 processor:
 Interfacing of 8255 with 8085 processor:
• The 8255 can be either memory mapped or I/O mapped in the
system. In the schematic shown in above is I/O mapped in the
system.
• Using a 3-to-8 decoder generates the chip select signals for I/O
mapped devices.
• The address lines A4, A5 and A6 are decoded to generate eight
chip select signals (IOCS-0 to IOCS-7) and in this, the chip select
IOCS- 1 is used to select 8255.
• The address line A7 and the control signal IO/M (low) are used as
enable for the decoder.
• The address line A0 of 8085 is connected to A0 of 8255 and A1 of
8085 is connected to A1 of 8255 to provide the internal addresses.
• The data lines D0-D7 are connected to D0-D7 of the processor to
achieve parallel data transfer.
Interfacing of 8255 with 8085 processor:
The I/O addresses allotted to the internal devices of 8255 are listed
in table.
THANK YOU