Unit 2: Register Transfer and

Microoperations
 Agenda
• Register Transfer
• Register Transfer Language
• Bus and Memory Transfers
• Arithmetic Microoperations
• Logic Microoperations
• Shift Microoperations
 Register transfer
Definition: Information transfer from one register to another is
described by a replacement operator is known as Register
transfer.
R2 ← R1
• This statement denotes a transfer of the content of register R1
into register R2.
• The transfer happens in one clock cycle.
• The content of the R1 (source) does not change.
• The content of the R2 (destination) will be lost and replaced by
the new data transferred from R1.
• We are assuming that the circuits are available from the
outputs of the source register to the inputs of the destination
register, and that the destination register has a parallel load
capability.
 Continued…
• Computer registers are designated by capital
letters (sometimes followed by numerals) to
denote the function of the register.
• For example:
• R1: processor register
• MAR: Memory Address Register (holds an address for a
memory unit)
• PC: Program Counter
• IR: Instruction Register
• SR: Status Register
 Register Transfer (continued)
• The individual flip-flops in an n-bit register are
numbered in sequence from 0 to n-1 (from the
right position toward the left position)

R1 7 6 5 4 3 2 1 0

Register R1 Showing individual bits

A block diagram of a register

 Register Transfer (continued)
Other ways of drawing the block diagram of a register:

15 0
PC

Numbering of bits

15 87 0
Upper byte PC(H) PC(L) Lower byte

Partitioned into two parts

 Register transfer with Control
function
• Conditional transfer occurs only under a control
condition.
• Representation of a (conditional) transfer
P: R2 ← R1
• A binary condition (P equals to 0 or 1) determines
when the transfer occurs
• The content of R1 is transferred into R2 only if P is
1.
Register transfer with Control function
Hardware implementation of a controlled transfer: P: R2 ← R1
Block diagram: Control P Load
R2 Clock
Circuit

R1

t t+1

Timing diagram Clock

Synchronized
Load
with the clock
Transfer occurs here
 Basic symbols for Register transfer

Basic Symbols for Register Transfers

Symbol Description Examples
Letters & Denotes a register MAR, R2
numerals
Parenthesis ( ) Denotes a part of a R2(0-7), R2(L)
register
Arrow ← Denotes transfer of R2 ← R1
information
Comma , Separates two R2 ← R1, R1 ← R2
microoperations
 Register Transfer Language (RTL)
• Digital systems are composed of modules that are
constructed from digital components such as registers,
decoders, arithmetic elements and control logic
• The modules are interconnected with common data and
control paths to from a digital computer system.
• Some of the digital components before from registers that
implement micro-operations.
• The operations executed on the data stored in the registers
are called micro-operations.
• A micro-operations is an elementary operation performed
on the information stored in one or more registers.
• Examples: shit, count, clear and load.
 Continued…
• The symbolic notation used to describe the micro-
operation transfer amongst register is called
REGISTER TRANSFER LANGUAGE.
• The word language is barrowed from programming
language.
• This programming language is a procedure for
writing symbols to specify a given computational
process.
• Register transfer means the availability of hardware
logic circuits that can perform a stated micro-
operation and transfer the same or another register.
 Continued…
• The internal hardware organization of a digital
computer is defined by specify the following:
• The set of registers it contains and their function
• The sequence of micro-operations performed on
the binary information stored in the registers
• The control that initiates the sequence of micro-
operations.
• Registers + Micro-operations Hardware + Control
Functions = Digital Computer.
• They use symbols rather than words to specify the
sequence of micro-operations.
 Continued…
• Definition: Register Transfer Language (RTL) is a
symbolic notation to describe the micro-operation
transfers among registers.
• A programming language is a procedure for writing a
symbols to specify a given computational process.
• RTL defines:
– Symbols for various types of micro-operations,
– Describe the associated hardware that
implements these micro-operations.
 Bus and Memory transfer
• Paths must be provided to transfer information
from one register to another.
• Rather than connecting wires between all the
registers common bus is used.
• A Common Bus System is a scheme for transferring
information between registers in a multiple-register
configuration.
• A bus: set of common lines, one for each bit of a
register, through which binary information is
transferred one at a time.
• Control signals determine which register is selected
by the bus during each particular register transfer.
 Bus Transfers
Register A Register B Register C Register D

Bus lines

Register D Register C Register B Register A

3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0

D3 D 2 D 1 D 0 C3 C2 C1 C0 B3 B2 B1 B0 A3 A2 A1 A0

D3 C3 B3 A3 D2 C2 B2 A2 D1 C1 B1 A1 D0 C0 B0 A0

3 2 1 0 3 2 1 0 3 2 1 0
3 2 1 0 S0
S0 S0 S0
MUX3 MUX2 MUX1 MUX0 S1
S1 S1 S1

4-Line Common Bus

 Continued…
• Multiplexers can be used to construct a common bus.
• Multiplexer selects the source register whose binary
information is then placed on the bus.
• The selection lines are connected to the selection
inputs of the multiplexers and choose the bits of one
register.
• In general, a bus system will multiplex k registers of
n bits, each to produce n line common bus.
• This requires n multiplexer – one for each bit.
• The size of each multiplexer must be k x 1.
 Continued…
• The transfer of information from a bus into one of
many destination registers is done:
– By connecting the bus lines to the inputs of all
destination registers and then:
– activating the load control of the particular
destination register selected
• We write: R2 ← C to symbolize that the content of
register C is loaded into the register R2 using the
common system bus
• It is equivalent to: BUS ←C, (select C)
R2 ←BUS (Load R2)
 Three-State Bus Buffers
• A bus system can be constructed with three-state
buffer gates instead of multiplexers.
• A three-state buffer is a digital circuit that
exhibits three states: logic-0, logic-1, and high-
impedance (Hi-Z)
Control input C

Normal input A Output B

Three-State Buffer
 Three-State Bus Buffers

C=1

Buffer
A B A B

C=0

Open Circuit
A B A B
 Three-State Bus Buffers
• Two of these states are signals equivalent to logic 1 and 0.
• The third state is a high – impedance state: this behaves
like an open circuit, which means the output is
disconnected and dose not have a logic significance.
• The three – state buffer gate has a normal input and
control input which determines the output state.
• With control 1, the output equals the normal output.
• With control 0, the gate goes to a high – impedance state.
• This enables a large number of three – state gate outputs
to be connected with wires to form common bus line
without endangering loading effects.
 Three-State Bus Buffers
S1 0
Select
S0 1
Bus line for bit 0
2×4 A0
Decoder 2
Enable E
3

B0

C0

Bus line with three-state buffer

(replaces MUX0 in the previous
diagram) D0

Bus line with three – state buffers

 Continued…
• Decoders are used to ensure that no more than one
control input is active at any given time.
• This circuit is replaced by multiplexer.
• To construct a common bus for four registers of n bits
each using three – state buffers, we need n circuits
with buffers in each.
• Only one decoder is necessary to select between the
four registers
• Designate a memory word by the letter M.
 Continued…
• It is necessary to specify the address of M when
writing memory transfer operations.
• Designate the address register by AR and the data
register by DR.
• The read operation can be stated as:
Read : DR  M [AR]
• The write operation can be stated as:
Write : M [AR]  R1
 Memory Transfer
• The address register (AR) is used to select a memory
address, and the data register (DR) is used to send and
receive data.
• Both these registers are connected to the internal bus.
• DR is a bridge between the internal BUS and the
memory data BUS.
• Memory can also be connected directly to the internal
BUS in theory.
 Continued…
• Most of the standard notations used for specifying
operations on memory transfer are stated below.
The transfer of information from a memory unit to the
user end is called a Read operation.
The transfer of new information to be stored in the
memory is called a Write operation.
A memory word is designated by the letter M.
We must specify the address of memory word while
writing the memory transfer operations.
The address register is designated by AR and the data
register by DR
 Continued…
• Thus, a read operation can be stated as:
1. Read: DR ← M [AR]
– The Read statement causes a transfer of information
into the data register (DR) from the memory word (M)
selected by the address register (AR).
• And the corresponding write operation can be stated as:
2. Write: M [AR] ← R1
– The Write statement causes a transfer of information
from register R1 into the memory word (M) selected by
address register (AR).
Figure: Block diagram showing connections to memory unit
 Micro-operations
• A micro-operation is an elementary operation performed
on the information stored in one or more registers.
• In Central Processing Units, micro-operations (also known
as micro-ops) are the functional or atomic, operations of
a processor.
• Usually, micro-operations perform basic operations on
data stored in one or more registers.
• Including transferring data between registers or between
registers and external buses of the central processing unit
(CPU), and performing arithmetic or logical operations on
registers.
 Categories of Micro-operations
• The Micro-operations in digital computers are of 4
types:
1. Register transfer Micro-operations.
2. Arithmetic Micro-operations.
3. Logic Micro-operations.
4. Shift Micro-operations.
 Arithmetic Micro-operations
• In general, the Arithmetic Micro-operations deals with the
operations performed on numeric data stored in the registers.
• The basic Arithmetic Micro-operations are classified in the
following categories:
 Addition
 Subtraction
 Increment
 Decrement
 Shift
• Some additional Arithmetic Micro-operations are classified as:
 Add with carry
 Subtract with borrow
 Transfer/Load, etc.
 Arithmetic Micro-operations
• The basic arithmetic micro-operations are:
addition, subtraction, increment, decrement,
and shift
• Addition Micro-operation:
R3 ←R1+R2
• Subtraction Micro-operation:
R3 ←R1-R2 or : 1’s complement

R3 ←R1+R2+1
 Arithmetic Micro-operations
• One’s Complement Micro-operation:
R2 ←R2
• Two’s Complement Micro-operation:
R2 ←R2+1
• Increment Micro-operation:
R2 ←R2+1
• Decrement Micro-operation:
R2 ←R2-1

cpe 252: Computer Organization 34

 Symbolic Representation Description

R3 ← R1 + R2 The contents of R1 plus R2 are

transferred to R3.

R3 ← R1 - R2 The contents of R1 minus R2 are

transferred to R3.

R2 ← R2' Complement the contents of R2 (1's

complement)

R2 ← R2' + 1 2's complement the contents of R2

(negate)

R3 ← R1 + R2' + 1 R1 plus the 2's complement of R2

(subtraction)

R1 ← R1 + 1 Increment the contents of R1 by one

R1 ← R1 – 1 Decrement the contents of R1 by
one
 Binary Adder
• The Add micro-operation requires registers that can hold
the data and the digital components that can perform
the arithmetic addition.
• A Binary Adder is a digital circuit that performs the
arithmetic sum of two binary numbers provided with any
length.
• A Binary Adder is constructed using full-adder circuits
connected in series, with the output carry from one full-
adder connected to the input carry of the next full-adder.
• The following block diagram shows the interconnections
of four full-adder circuits to provide a 4-bit binary adder.
 Arithmetic Micro-operations
B A B
Binary
A
Adder
B A B A
3 3 2 2 1 1 0 0

C4 C3 C2 C1 C0
FA FA FA FA

S3 S2 S1 S0

4-bit binary adder (connection of FAs)

• The augends bits (A) and the addend bits (B) are designated by
subscript numbers from right to left, with subscript '0' denoting
the low-order bit.
• The carry inputs starts from C0 to C3 connected in a chain
through the full-adders. C4 is the resultant output carry
generated by the last full-adder circuit.
• The output carry from each full-adder is connected to the input
carry of the next-high-order full-adder.
• The sum outputs (S0 to S3) generates the required arithmetic
sum of augends and addend bits.
• The n data bits for the A and B inputs come from different source
registers. For instance, data bits for A input comes from source
register R1 and data bits for B input comes from source register
R2.
• The arithmetic sum of the data inputs of A and B can be
transferred to a third register or to one of the source registers
(R1 or R2).
 Binary Adder- Subtractor
• The Subtraction micro-operation can be done easily
by taking the 2's compliment of addend bits and
adding it to the augends bits.
• The Arithmetic micro-operations like addition and
subtraction can be combined into one common circuit
by including an exclusive-OR gate with each full
adder.
• The block diagram for a 4-bit adder-subtractor circuit
can be represented as:
Figure: 4-bit adder-
subtractor
• When the mode input (M) is at a low logic, i.e. '0', the
circuit act as an adder and when the mode input is at
a high logic, i.e. '1', the circuit act as a subtractor.
• The exclusive-OR gate connected in series receives
input M and one of the inputs B.
• When M is at a low logic, we have B⊕ 0 = B.
The full-adders receive the value of B, the input carry
is 0, and the circuit performs A plus B.
• When M is at a high logic, we have B⊕ 1 = B' and C0
= 1.
The B inputs are complemented, and a 1 is added
through the input carry. The circuit performs the
operation A plus the 2's complement of B.
Binary Incrementer and Decrementer
• The increment micro-operation adds one binary value
to the value of binary variables stored in a register.
• For instance, a 4-bit register has a binary value 0110,
when incremented by one the value becomes 0111.
• A binary decrementer can be implemented by adding
1111 to the desired register each time.
• The increment micro-operation is best implemented
by a 4-bit combinational circuit incrementer.
• A 4-bit combinational circuit incrementer can be
represented by the following block diagram.
Figure: Binary Incrementer
• A logic-1 is applied to one of the inputs of least
significant half-adder, and the other input is
connected to the least significant bit of the number
to be incremented.
• The output carry from one half-adder is connected
to one of the inputs of the next-higher-order half-
adder.
• The binary incrementer circuit receives the four bits
from A0 through A3, adds one to it, and generates
the incremented output in S0 through S3.
• The output carry C4 will be 1 only after
incrementing binary 1111.
 Logic Micro-operations
• The logic micro-operation is used for specifying
binary operation for the strings of bits stored in
the register.
• Here, each bit of register is treated as a separate
binary variable. In other words, each individual bit of
a register operates with corresponding register bit.
• Various logical operation like OR, AND, NAND, and
other logical operators. Special symbols are used for
representing OR and AND operators with v and ^
respectively.
 Example
• Let us consider that there are two register R1 and R2,
each with four bit.
• Let register R1 have 1010 and R2 have 1100.
• If OR micro-operation is performed on
these registers and the result is stored in
the register P.
• Then this operation can be represented as:
P R1 + R2
Table: Represents the OR operation on R1 and R2
Bit 3 Bit 2 Bit 1 Bit 0

A 1 0 1 0

B 1 1 0 0

A OR B 1 1 1 0
Table : Represents the AND operation on R1 and R2
Bit 3 Bit 2 Bit 1 Bit 0

A 1 0 1 0

B 1 1 0 0

A AND B 1 0 0 0
 Logic Micro-operations
The four basic micro-operations
AND Micro-operation
• Symbol: 

• Gate:

• Example: 1001102  10101102 = 00001102

 Logic Micro-operations
The four basic micro-operations
Complement (NOT) Micro-operation
• Symbol:


• Gate:

• Example: 10101102 = 01010012

 Logic Micro-operations
The four basic micro-operations
XOR (Exclusive-OR) Micro-operation
• Symbol: 

• Gate:

• Example: 1001102  10101102 = 11100002

 Logic Micro-operations
Other Logic Micro-operations
Selective-set Operation
• Used to force selected bits of a register into
logic-1 by using the OR operation

• Example: 01002  10002 = 11002

In a processor register Loaded into a register from

memory to perform the selective-
set operation
 Logic Micro-operations
Other Logic Micro-operations
Selective-complement (toggling) Operation
• Used to force selected bits of a register to be
complemented by using the XOR operation

• Example: 00012  10002 = 10012

In a processor register Loaded into a register from

memory to perform the selective-
complement operation
 Logic Micro-operations
Other Logic Micro-operations
Insert Operation
• Step1: mask the desired bits
• Step2: OR them with the desired value

• Example: suppose R1 = 0110 1010, and we desire

to replace the leftmost 4 bits (0110) with 1001
then:
– Step1: 0110 1010  0000 1111
– Step2: 0000 1010  1001 0000
 R1 = 1001 1010
 Logic Micro-operations
Other Logic Micro-operations
NAND Micro-operation

• Symbols:  and


• Gate:

• Example: 1001102  10101102 = 11110012

 Logic Micro-operations
Other Logic Micro-operations
NOR Micro-operation

• Symbols:  and


• Gate:

• Example: 1001102  10101102 = 00010012

 Logic Micro-operations
Other Logic Micro-operations
Set (Preset) Micro-operation
• Force all bits into 1’s by ORing them with a value
in which all its bits are being assigned to logic-1
• Example: 1001102  1111112 = 1111112
Clear (Reset) Micro-operation
• Force all bits into 0’s by ANDing them with a value
in which all its bits are being assigned to logic-0
• Example: 1001102  0000002 = 0000002
 Logic Micro-operations
Hardware Implementation
• The hardware implementation of logic micro-
operations requires that logic gates be
inserted for each bit or pair of bits in the
registers to perform the required logic
function
• Most computers use only four (AND, OR, XOR,
and NOT) from which all others can be
derived.
 Logic Micro-operations
Hardware Implementation
S1
4×1 Operati-
S0
MUX S1 S0 Output on
Ai
0 0 E=AB XOR
Bi
0
0 1 E=AB OR

1 0 E=AB AND
1 Ei
1 1 E=A Complem
ent

3 This is for one bit i

60
 Shift Micro-operations
• Shift Micro Operations in computer architecture are
those which are used in serial shifting of data present
in a register.
• We can also say that Shift micro Operations move or
shift data in a register that is, one bit at a time either
left or right from its original position.
• Also used in conjunction with arithmetic, logic, and
other data-processing operations
• The contents of the register can be shifted to the left or
to the right.
• As being shifted, the first flip-flop receives its binary
information from the serial input
• Let us take two values, 0 and 8 in two different
registers A and B. We perform addition on both
the registers before shift operation and after
doing shift operation.
• As we know that 0 has its binary value ‘0000’ and
8 as ‘1000’, and in registers binary values are
stored. So if we add these two values, we get.
0000 (0 in register A)
+1000 (8 in register B)
1000 (New value is 8 after addition
without performing shift operation)
• But, when we perform shift left operation that is,
shifting one bit towards left on 8, 1000 changes
to 0000 as follows

• So, after shifting one bit towards left, as shown

in the above representation, a 0 will enter from
the right end and 1 in the left most end will be
removed from the 4 digit value. After shifting we
get
• So, if we add now, the result changes to zero as 8
changed to zero after shift left operation.
0000 (0 in register A)
+0000 (8 changed to 0 due to shift
left operation performed on register B)
0000 (The value changed to be 0 instead of 8).
• So, without the need of clearing the value first in
the register and then inserting a new value, we
directly change the value in the register by
performing shift operation.
 Types of Shift Micro Operations
• Arithmetic Shift Micro Operation
• Logical Shift Micro Operation
• Circular Shift Micro Operation
Arithmetic Shift Micro Operation
• Arithmetic Shift Operation shifts signed (positive or
negative) binary numbers either left or right by
multiplying or dividing by 2.
• In RTL (RTL stands for Register Transfer Language), we
can represent this arithmetic shift micro operations as
– R ← ashl R (arithmetic shift left R (register))
– R ← ashr R (arithmetic shift right R (register))
Figure: Block diagram showing Arithmetic shift left operation

Figure: Block diagram showing Arithmetic shift right operation

 Logical Shift Micro Operation
• A Logical Shift Micro Operation transfers a 0 (zero)
through the serial input, either from left or right
depending on the type.
• For, logical shift left micro operation, 0 (zero) is
transferred through the right of the data and for the
logical shift right micro operation, 0 (zero) is transferred
through the left of the data as shown in the figures
below.
• Register Transfer Language (RTL) for the logical shift
micro operations can be written as:
– R ← shl R (shift left register (R)).
– R ← shr R (shift right register (R)).
Figure: Block diagram showing the logical shift right micro
operation on the data in a register

Figure: Block diagram showing the logical shift right micro

operation on the data in a register
 Circular Shift Micro Operation
• A Circular Shift micro operation performs the shifting of
bits from one end of the register to the other end of the
register.
• In Circular shift left operation, the left most bit in the
register is transferred to the right most end and in the
circular shift right operation, the right most bit in the
register is transferred or shifted to the left most end of
the register as shown in the figures below:
• Register Transfer Language for the Circular Shift micro
operations can be written as:
– R  cil R (circular shift left register (R)).
– R  cir R (circular shift right register (R)).
 Block diagram showing
circular shift left micro
operation

Block diagram showing

circular shift right micro
operation
• Shift micro operations that are used to shift data in a
register are as follows irrespective of their type that
is, either arithmetic or logical etc. The following are
the list of all shift micro operations.
– SHL (Logical Shift Left)
– SHR (Logical Shift Right)
– ASHL (Arithmetic Shift Left)
– ASHR (Arithmetic Shift Right)
– CIL (Circular Shift Left)
– CIR (Circular Shift Right)
• All the above Operations are shift operations in
computer organization and are operated on data in
registers performing logical, arithmetic and circular
shift operations.
Memory Organization
 Introduction
• Memory unit is essential component of digital computer
since it is needed for storing programs and data.
• Memory unit that communicates directly with CPU is
called Main memory.
• Devices that provide backup storage is called auxiliary
memory.
• Only programs and data currently needed by processor
reside in the main memory.
• All other information is stored in auxiliary memory and
transferred to main memory when needed.
• Key characteristics of computer memory system is shown
here.
Figure : Memory Hierarchy in Computer System
Memory Hierarchy
 Continued…
• Memory hierarchy system consist of all storage
devices from auxiliary memory to main memory to
cache memory
• As one goes down the hierarchy :
– Cost per bit decreases.
– Capacity increases.
– Access time increases.
– Frequency of access by the processor decreases.
 Continued…
• CPU Register - also known as Internal Processor
Memory. The data or instruction which has to be
executed are kept in these registers.
• The Cache Memory is employed in computer system
to compensate for the speed differential between main
memory access time and processor logic.
• The cache is used for storing segments of programs
currently being executed in the CPU and temporary
data frequently needed for the present calculations.
• By making program and data available at a rapid rate,
it is possible to increase the performance rate of the
computer.
 Memory Management System
• Many operating system are designed to enable the CPU
to process a number of independent programs
concurrently - known as multiprogramming.
• Sometimes a program are too long to be accommodated
in total space available in main memory. A program with
its data normally resides in auxiliary memory.
• When the program or a segment of program is to be
executed, it is transferred to main memory to be executed
by the CPU.
• The part of the computer system that supervise the flow
of information between auxiliary memory and main
memory is called the memory management system.
 Main Memory
• It is the memory used to store programs and data during the
computer operation.
• The principal technology used for main memory is based on
semiconductor integrated circuit.
• It consists of RAM and ROM chips.
• The Integrated circuit chips are available in two possible
operating modes:
– Static
– Dynamic
• The Static RAM consists essentially of internal flip-flop that
store the binary information.
• The dynamic RAM stores the binary information in form of
electronic charges that are applied to capacitors.
 Continued…
• The stored charge on the capacitor tend to discharge
with time and the capacitors must be periodically
recharged by refreshing the dynamic memory.
• The static RAM is easier to use and has shorter read
and write cycles and used in cache.
• The dynamic RAMs are used for implementing the
main memory.
 DRAM SRAM

Uses capacitor for storing Uses Flip flop

information
More cells per unit area due Needs more space for same
to smaller cell size. capacity
Cheap and smaller in size Expensive and bigger in size

Slower and analog device Faster and digital device

Requires refresh circuit No need

Used in main memory Used in cache

 Continued…
• ROM is uses random access method.
• It is used for storing programs that are permanent
and the tables of constants that do not change.
• ROM store program called bootstrap loader whose
function is to start the computer software when the
power is turned on.
• When the power is turned on, the hardware of the
computer sets the program counter to the first
address of the bootstrap loader.
 Continued...
• For the same size chip it is possible to have more
bits of ROM than of RAM, because the internal
binary cells in ROM occupy less space than in
RAM,
• For this reason the diagram specifies 512 byte
ROM and 128 bytes RAM.
 Memory Address Map
• Designer must specify the size and the type(RAM or
ROM) of memory to be used for particular
application.
• The addressing of the memory is then established by
means of table called memory address map that
specifies the memory address assign to each chip.
• Let us consider an example in which computer needs
512 bytes of RAM and ROM as well and we have to
use the chips of size 128 bytes for RAM and 512 bytes
for ROM.
 Auxiliary Memory
• The Most common auxiliary memory devices used in
computer system are magnetic disk and tapes.
• Other components used, but not as frequently, are
magnetic drums, magnetic bubble memory, and optical
disks.
• The average time required to reach a storage location in
memory and obtain its contents is called the access time.
• In electromechanical devices with moving parts such as
disks and tapes, the access time consists of seek time
required to position the read-write head to a location and
a transfer time required to transfer data to or from the
devices.
 Associative Memory
• An assembler program searches the symbol address table
in order to extract the symbol’s binary equivalent.
• The number of accesses to memory depends on the
location of the item and the efficiency of search algorithm.
• Many search algorithm have been developed to minimize
the number of access while searching for an item in a
random or sequential access memory.
• The time required to find an item stored in memory can be
reduced considerably if stored data can be identified by
the content of the data itself rather than an address.
• A memory unit accessed by content is called an associative
memory or content addressable memory(CAM).
• To search particular data in memory, data is read from
certain address and compared if the match is not found
content of the next address is accessed and compared.
• This goes on until required data is found. The number
of access depend on the location of data and efficiency
of searching algorithm.
• The searching time can be reduced if data is searched
on the basis of content.
• This type of memory is accessed simultaneously and in
parallel on the basis of data content.
• Memory is capable of finding empty unused location to
store the word.
• These are used in the application where search time is
very critical and must be very short.
 Continued…
• It consists memory array of m words with n bits per
words.
• Argument register A and key register K have n bits
one for each bit of word.
• Match register has m bits, one for each memory
word.
• Each word in memory is compared in parallel with
the content of the A register. For the word that match
corresponding bit in the match register is set.
• Key register provide the mask for choosing the
particular field in A register.
 Continued…
• The entire content of A register is compared if key
register content all 1’s.
• Otherwise only bit that have 1 in key register are
compared.
• If the compared data is matched corresponding bits
in the match register are set.
• Reading is accomplished by sequential access in
memory for those words whose bit are set.
Continued…
 Match Logic
• Let us neglect the key register and compare the
content of argument register with memory
content.
• Word i is equal to argument in A if Aj=Fij for
j=1,2,3,4……..n
• The equality of two bits is expressed as

• xj =1 if bits are equal and 0 otherwise.

 Continued…
• Let us include key register. If Kj=0 then there is no
need to compare Aj and Fij.
• Only when Kj=1, comparison is needed.
• This achieved by ORing each term with Kj.
 Read Operation
• If more than one word match with the content, all
the matched words will have 1 in the
corresponding bit position in match register.
• Matched words are then read in sequence by
applying a read signal to each word line.
• In most application, the associative memory
stores a table with no two identical items under a
given key.
 Write Operation
• If the entire memory is loaded with new information
at once prior to search operation then writing can be
done by addressing each location in sequence.
• Tag register contain as many bits as there are words
in memory.
• It contain 1 for active word and 0 for inactive word.
• If the word is to be inserted, tag register is scanned
until 0 is found and word is written at that position
and bit is change to 1.
 Cache Memory
• A typical computer program flows in a straight-line fashion
with program loops and subroutine calls encountered
frequently.
• Analysis of a large number of typical programs has been
shown that the reference to memory at any given interval
of time tend to be confined within a few localized areas in
memory. This phenomenon is known as the property of
locality of reference.
• If the active portions of the program and data are placed in
a fast small memory, the average memory access time can
be reduced, thus reducing the total execution time of
program. Such memory is known as Cache memory.
 Continued…
• It is placed in between the main memory and the CPU.
• When the CPU need to access the memory it first
search in cache. If word is found, it is read.
• If the word is not found, it is read from main memory
and a block of data is transferred from main memory
to cache which contain the current word.
• If the word is found in cache, it is said hit. If the word is
not found, it is called miss.
• Performance of cache is measured in terms of hit ratio
which ratio of total hit to total memory access by CPU.
 Mapping Techniques
• The transformation of data from main memory to
cache is known as mapping process.
• Three types of mapping procedures are:
 Associative Mapping
 Direct Mapping
 Set-Associative Mapping
 Associative Mapping
• Fastest and most flexible cache organization uses
associative memory.
• It stores both address and content of memory word.
• Address is placed in argument register and memory is
searched for matching address.
• If address is found corresponding data is read.
• If address is not found, it is read from main memory and
transferred to cache.
• If the cache is full, an address- word pair must be
displaced.
• Various algorithm are used to determine which pair to
displace. Some of them are FIFO(First In First Out),
LRU(Least Recently Used) etc.
Associative Mapping
 Direct Mapping
• CPU address is divided into two fields tag and index.
• Index field is required to access cache memory and total
address is used to access main memory.
• If there are 2^k words in cache and 2^n words in main
memory, then n bit memory address is divided into two
parts. k bits for index field and n-k bits for tag field.
• When CPU generates memory request, index field is used to
access the cache.
• Tag field of the CPU address is compared with the tag in the
word read. If the tag match, there is hit.
• If the tag does not match, word is read from main memory
and updated in cache.
Direct Mapping Cache Organization
 Continued…
• This example use the block size of 1.
• The same organization can be implemented for block
size 8.
• The index field is divided into two parts: block field and
word field.
• In 512 word cache there are 64 blocks of 8 words
each(64*8=512).
• Block is specified with 6 bit field and word within block
with 3 bit field.
• Every time miss occur, entire block of 8 word is
transferred from main memory to cache.
 Set-Associative Mapping
• In direct mapping two words with same index in their
address but different tag values can’t reside
simultaneously in memory.
• In this mapping, each data word is stored together with
its tag and number of tag-data items in one word of the
cache is said to form set.
• In general, a set associative cache of set size k will
accommodate k words of main memory in each word of
cache.
• When a miss occur and the set is full, one of the tag data
item is replaced with new value using various algorithm.
 Writing into Cache
• Writing into cache can be done in two ways:
 Write through
 Write Back
• In write through, whenever write operation is
performed in cache memory, main memory is also
updated in parallel with the cache.
• In write back, only cache is updated and marked by the
flag. When the word is removed from cache, flag is
checked if it is set the corresponding address in main
memory is updated.
 Cache Initialization
• When power is turned on, cache contain invalid data
indicated by valid bit value 0.
• Valid bit of word is set whenever the word is read from
main memory and updated in cache.
• If valid bit is 0, new word automatically replace the
invalid data.
 Virtual Memory
• In a memory hierarchy system, program and data are
first stored in auxiliary memory.
• Portion of a program or data are brought into main
memory as they are needed by the CPU.
• Virtual memory is a concept used in computer that
permit the user to construct a program as though large
memory space is available equal to auxiliary memory.
• It give the illusion that computer has large memory even
though computer has relatively small main memory.
• It has mechanism that convert generated address into
correct main memory address.
Address Space and Memory Space
• An address used by the programmer is called virtual
address and set of such address is called Address
space.
• An address in main memory is called physical address.
The set of such location is called Memory space.
 Address Mapping Using Pages
• The main memory is broken down into groups of equal
size called blocks.
• Term pages refers to groups of address space of same
size.
• Although page and block are of equal size, page refer
to organization of address space and block represent
the organization of memory space.
• The term page frame is sometimes used to denote
block.
 Page Replacement
• The program is executed from main memory until page
required is not available.
• If page is not available, this condition is called page
fault. When it occurs, present program is suspended
until the page required is brought into main memory.
• If main memory is full, pages to remove is determined
from the replacement algorithm used.