System on Chip Architecture

James E. Stine
Design modeling

1 Oklahoma State University

Elmore delay example

R2 R4

C2 C4

R1 R3 R5

C1 C3 C5

τd5 = R1C1 + R1C2 + (R1+R3)C3 + (R1+R3)C4 + (R1+R3+R5)C5

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Wire Delay

• Wires are a distributed RC network.

• Break into RC sections
– There are 3 different kinds
R

R
C

L-model C/2 C/2

R/2 R/2
p -model
C

T-model
[CMOS VLSI Design Weste/Harris]

3
Lumped Element Models

• Wires are a distributed system

– Approximate with lumped element models

N segments
R R/N R/N R/N R/N
C C/N C/N C/N C/N

R R R/2 R/2

C C/2 C/2 C

L-model p -model T-model

[CMOS VLSI Design Weste/Harris]

• 3-segment π-model is accurate to 3% in simulation

• L-model needs 100 segments for same accuracy!
• Use single segment p-model for Elmore delay
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Why use Pi model

• Let’s look another example.

• Calculate the Elmore delay or first moment
– td

• Elmore delay of T and Pi models is ½ RT CT even for one

section
– Estimate is unchanged if you add sections.

• Elmore delay of L model is RT CT for one section

– Adding sections reduces the delay
– (N+1)/N ½ RT CT

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Example

• Metal2 wire in 180 nm process

– 5 mm long 5 103
6
 15.625  10 3

– 0.32 µm wide 0.32 10

• Construct a 3-segment p-model

– R = 0.05 Ω/  R = 781 Ω = 3 ∙ 260.33 Ω
– Cpermicron = 0.2 fF/ μm  C = 1 pF = 6 ∙ 0.167 fF

260 Ω 260 Ω 260 Ω

167 fF 167 fF 167 fF 167 fF 167 fF 167 fF

[CMOS VLSI Design Weste/Harris]

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Wire RC Delay

• Estimate the delay of a 10x inverter driving a 2x inverter at the

end of the 5mm wire from the previous example.
– R = 2.5 kΩ* μm for gates
– Unit inverter: 0.36 μm nMOS, 0.72 μm pMOS
2.5∙103 [Ω* μm] 781 W (0.36+0.72)∙2∙2 [fF]
0.36∙10 [μm]

690 W 500 fF 500 fF 4 fF

Driver Wire Load

Elmore Delay: tpd = 690Ω∙500fF + (690Ω + 781Ω)∙(500fF + 4fF)

tpd = 1.1 ns [CMOS VLSI Design Weste/Harris]

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Crosstalk

• A capacitor does not like to change its voltage instantaneously.

• A wire has high capacitance to its neighbor.

– When the neighbor switches from 10 or 01, the wire tends to
switch too.
– Called capacitive coupling or crosstalk.

• Crosstalk effects
– Noise on nonswitching wires
– Increased delay on switching wires

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Crosstalk Delay

• Assume layers above and below on average are quiet

– Second terminal of capacitor can be ignored
– Model as Cgnd = Ctop + Cbot

• Effective Cadj depends on behavior of neighbors

– Miller effect

B DV Ceff(A) MCF

Constant VDD Cgnd + Cadj 1

A B
Cadj
Switching with A 0 Cgnd 0
Cgnd Cgnd
Switching opposite A 2VDD Cgnd + 2 Cadj 2
[CMOS VLSI Design Weste/Harris]

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Crosstalk Noise

• Crosstalk causes noise on nonswitching wires

• If victim is floating:
– model as capacitive voltage divider

Aggressor

DVaggressor
Cadj
Victim
Cgnd-v DVvictim

Cadj
DVvictim  DVaggressor
Cgnd v  Cadj [CMOS VLSI Design Weste/Harris]

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Driven Victims

• Usually victim is driven by a gate that fights noise

– Noise depends on relative resistances
– Victim driver is in linear region, agg. in saturation
– If sizes are same, Raggressor = 2-4 x Rvictim

Raggressor
Aggressor
Cgnd-a
DVaggressor
Cadj
Rvictim Victim
Cgnd-v DVvictim

Cadj 1  aggressor Raggressor  Cgnd a  Cadj 

DVvictim  DVaggressor k 
Cgnd v  Cadj 1 k  victim Rvictim  Cgnd v  Cadj 
[CMOS VLSI Design Weste/Harris]

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Coupling Waveforms

• Simulated coupling for Cadj = Cvictim

Aggressor
1.8

1.5

1.2

Victim (undriven): 50%

0.9

0.6
Victim (half size driver): 16%

Victim (equal size driver): 8%

0.3 Victim (double size driver): 4%

0
0 200 400 600 800 1000 1200 1400 1800 2000

t(ps) [CMOS VLSI Design Weste/Harris]

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Repeaters

• R and C are proportional to l

• RC delay is proportional to l2
– Unacceptably great for long wires

Break long wires into N shorter segments.

Drive each one with an inverter or buffer.
Wire Length: l

Driver Receiver

N Segments
Segment
l/N l/N l/N

Driver Repeater Repeater Repeater Receiver

[CMOS VLSI Design Weste/Harris]

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Repeater Design

• How many repeaters should we use?

• How large should each one be?
• Equivalent Circuit
– Wire length l
– Wire Capacitance Cw*l, Resistance Rw*l
– Inverter width W (nMOS = W, pMOS = 2W)
– Gate Capacitance C’*W, Resistance R/W

RwlN

R/W
Cwl2N Cwl2N C'W
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Repeater Results

• Write equation for Elmore Delay

– Differentiate with respect to W and N
– Set equal to 0, solve

l 2 RC 

N RwCw

 
t pd ~60-80 ps/mm
 2 2 RCRwCw
l in 180 nm process

RCw
W
RwC

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