Professional Documents
Culture Documents
Presenter
Abu Shohel Ahmed
Md. Kamrul Abedin Tarafder
Debashis roy
History
Programmable Read Only Memory (PROM)
address line as input
data line as output
Problem:
don’t require all the logic combination in input.
Programmable Logic Array (PLA)
- Programmable AND plane followed by
programmable or wired OR plane.
- Sum of product form
- Two level programming adds delay (problem)
Next -
PAL ( Programmable array logic)
- Programmable AND plane and fixed OR
plane.
- All these PLA and PAL are Simple
programmable logic devices.
- Logic plane structure grows rapidly with
number of inputs( problem)
Next
To mitigate the problem
Complex programmable logic devices
(CPLD)
-programmably interconnect multiple
SPLDs.
- Extending to higher density difficult
(problem)
- Less flexibility (problem)
Comparison
What is FPGA?
The way
programmable
switches and
wiring segments
are positioned for
interconnections.
Core Elements:
c. Wire segment
d. Track
e. Routing Channel
f. Connection Block
g. Switch Block
Why better ?
-FPGA programmed using electrically
programmable switches
-Routing architectures are complex.
-Logic is implemented using multiple levels
of lower fanin gates.
-Shorter time to market
-Ability to re-program in the field to fix bugs
-Lower non-recurring engineering costs
FPGA Disadvantage
FPGAs are generally slower than their
application-specific integrated circuit
(ASIC)
Can't handle as complex a design, and
draw more power.
FPGA Design and Programming
To define the behavior of the FPGA the user provides a
hardware description language (HDL) or a schematic
design.
Then, using an electronic design automation tool, a
technology-mapped net list is generated.
The netlist can then be fitted to the actual FPGA architecture
using a process called place-and-route.
The user will validate the map, place and route results via
timing analysis, simulation, and other verification
methodologies.
Once the design and validation process is complete, the
binary file generated used to configure the FPGA.
Application
1. Reconfigurable computing.
2. Applications of FPGAs include DSP,
software-defined radio.
3. The inherent parallelism of the logic
resources on the FPGA allows for
considerable compute throughput.
FPGA Optimization
DAG map: Graph based FPGA mapping for delay optimization
DAG-Map reduces both the network depth and the number of
lookup-tables.
Problem Formulation:
A Boolean network can be represented as a directed acyclic
graph (DAG) where each node represents a logic gate and
there is a directed edge (i, j) if the output of gate i is an input of
gate j.
A primary input (PI) node has no incoming edge and a primary
output (PO) node has no outgoing edge.
We use input (v ) to denote the set of nodes which supply
inputs to gate
DAG-Map Algorithm
The DAG-Map algorithm consists of three
major steps.
- The first step transforms an arbitrary
boolean network into a two-input network.
- The second step maps the two-input
network into a K-LUT FPGA network with
minimum delay.
- The third step performs a postprocessing
area optimization of the FPGA network without
increasing the network delay.
Fi rst S tep: Trans for ming
Ar bitr ary Netw orks into T wo-
Input Ne twor ks
THANKS