Micro Lec Note1

‫ريزپردازنده ها‬
Microprocessors
Spring 2005
hsabaghianb @ kashanu.ac.ir Microprocessors 1-1

Books
 The Z80 Microprocessor , Hardware , Software
programming & interfacing
 Author: Burry B. Brey
 Translator: Hossein Nia
 Publisher: Astane Ghodse Razavi(Beh Nashr

Books
 Microcompiuter and Microprocessor : the
8080 , 8085 , Z-80 Programming , interfacing
and trubleshooting
 Publisher: Nass
Pub.Date: 1381
Edition Turn: 3
ISBN: 964-6264-43-4-3
Pages: 719
Author: John E . UffenbeckTranslator: Mahmmod
Dayani

Books
 The 80x86 IBM PC and compatible
computers (Design and interfacing of the
IBM PC PS and compatible)
Publisher: Baghani
Pub.Date: 1379
Edition Turn: 2
ISBN: 964-91532-3-3
Pages: 760
Author: Mohammad Ali . Mazidi
Janice Gillispie . MazidiTranslator: Dr.
Sepidnam

Books
 Microcontroller 8051
Publisher: Baghani
Pub.Date: 1380
ISBN: 964-7343-00-0
Pages: 380
Author: Mohammad ali Mazidi
Jonis Glispi MazidiTranslator: Dr.
Sepidnam

Books
 The 8051 Microcontroller
Publisher: Baghani
Pub.Date: 1380
Publishing Turn: 5
Edition Turn: 3
ISBN: 964-91532-2-5
Pages: 383
Author: Iscott Makenzi
Translator: Rezaei Nia ,Darbandi Azar

Intruduction
 Microprocessor (uP)(MPU)
 A uP is a CPU on a single chip.
 Components of CPU
ALU, instruction decoder, registers, bus
control circuit, etc.
 Micro-computer (u-Computer)
 small computer
 uP + peripheral I/O + memory specifically for data
acquisition and control applications
 Microcontroller (uC)
 u-Computer on a single chip of silicon

uP vs. uC
 A uP
 only is a single-chip CPU
 bus is available
 RAM capacity, num of port is seletable
 RAM is larger than ROM (usually)
 A uC
 contains a CPU and RAM,ROM ,Prepherals, I/O port in a single
IC
 internal hardware is fixed
 Communicate by port
 ROM is larger than RAM (usually)
 Small power consumption
 Single chip, small board
 Implementation is easy
 Low cost

uP vs. uC – cont.
 Applications
 uCs are suitable to
control of I/O
devices in designs
requiring a minimum
component
 uPs are suitable to
processing
information in
computer systems.

uP vs. uC – cont.
 uC is easy to use and design.
 Only single chip can be a complete system
 interfacing to other devices,
 for example, motors, displays, sensors, and
communicate with PC.
 In contrast, similar system that builds from
uP would require a lot of additional units,
 such as RAM, UART, I/O , TIMER and etc.

uC is a Reusable Hardware
 Logic circuit provides limited function for one

single design. In order to change circuit’s
functionality, we need to redesign the circuits.
 uC can reprogram and change functionality of
every port, input to output or digital to analog
on the fly.

uCs
 Many uCs are existing right now.
 8051, 68HC11, MSP430, ARM series, and etc.
 We may widely divide it with how it is designed
 RISC/CISC architecture.
 What is the main difference between
RISC/CISC?
 Does it make any difference to our application?

The Microprocessor (MPU)
 The uP is the ‘brain of the microcomputer’

 Is a single chip which is capable of
 processing data
 controlling all of the components which make up the
microcomputer system
 µP used to sequence executions of instructions
that is in memory
 uP Fetch , Decode , and Execute the
instruction
 The internal architecture of the microprocessor
is complex.

The Microprocessor (MPU)
 microprocessor (MPU) typically contains

 Registers: Temporary storage locations for program
instruction or data.
 The Arithmetic Logic unit (ALU): This part of the MPU
performs both arithmetic and logical operations
 Timing and Control Circuits: that keep all of the other
parts of system (Regs, ALU, memory & I/O) working
together in the right time sequence

Microcomputers
 All Microcomputers consist of (at least) :
 1. Microprocessor Unit (MPU)
 2. Program Memory (ROM)
 3. Data Memory (RAM)
 4. Input / Output ports
 5. Bus System
 (and Software)
 MPU is the brain of microcomputer

Microcomputers

The Input/Output (I/O) System
 I/O is the link between the MPU and the outside

world.
 An input port is a circuit through which an

external device can send signals (data?) to the
MPU.
 An output port is a circuit that allows the MPU to

send signals (data?) to external devices.
 I/O ports connect both digital and analogue

devices by DAC and ADC

Bus
 A Bus is a common communications pathway used to
carry information between the various elements of a
computer system
 The term BUS refers to a group of wires or
conduction tracks on a printed circuit board (PCB)
though which binary information is transferred from
one part of the microcomputer to another
 The individual subsystems of the digital computer are

connected through an interconnecting BUS system.

Bus
There are three main bus groups

 ADDRESS BUS
 DATA BUS
 CONTROL BUS

Data Bus
 The Data Bus carries the data which is transferred
throughout the system. ( bi-directional)
 Examples of data transfers

 Program instructions being read from memory into MPU.
 Data being sent from MPU to I/O port
 Data being read from I/O port going to MPU
 Results from MPU sent to Memory
 These are called read and write operations

Address Bus
 An address is a binary number that identifies a
specific memory storage location or I/O port
involved in a data transfer
 The Address Bus is used to transmit the address

of the location to the memory or the I/O port.
 The Address Bus is unidirectional ( one way ):

addresses are always issued by the MPU.

Control Bus
 The Control Bus: is another group of signals whose
functions are to provide synchronization ( timing
control ) between the MPU and the other system
components.
 Control signals are unidirectional, and are mainly

outputs from the MPU.
 Example Control signals

 RD: read signal asserted to read data into MPU
 WR: write signal asserted to write data from MPU

Main memory
 The duties of the memory are :
 To store programs
 To provide data to the MPU on request
 To accept result from the MPU for storage
 Main memory Types
 ROM : read only memory. Contains program
(Firmware). does not lose its contents when
power is removed (Non-volatile)
 RAM: random access memory (read/write
memory) used as variable data, loses contents
when power is removed volatile. When power up
will contain random data values

Read-Only Memory
 uP can read instructions from ROM quickly

 Cannot write new data to the ROM
 ROM remembers the data, even after
power cycled
 Typically, when the power is turned on, the
microprocessor will start fetching
instructions from the still-remembered
program in ROM (bootstrap )

Available ROMs
 Masked ROM or just ROM

 PROM or programmable ROM(once only)
 EPROM (erasable via ultraviolet light)
 Flash (can be erased and re-written about 10000
times, usually must write a whole block not just 1
byte or 2 bytes, slow writing, fast reading)
 EEPROM (electrically erasable read-only memory,
also known as EEROM—both reading and writing
are very slow but can program millions of times…
useless for storing a program but good for say
configuration information.

ROM
A0 D0
A1 D1
m+1 bit A2 D2 n+1 bit

Address Data
Am 2m1  (n  1)
Dn
m 1
Capacity : 2 ROM
PROM
EEPROM
OE : Output Enable
connect to RD of uP
CE (CS ) : Chip Enable

to Address decoder CE OE

Timing Diagram for a Typical ROM
A0-Am
D0-Dn
CE
OE
OE falls to data valid

Addr valid to data valid

27XX EPROM U3
10 11
9 A0 O0 12
U1 U2 A1 O1
8 13
7 A2 O2 15
8 9 8 9 A3 O3
7 A0 O0 10 A0 O0 6 16
A1 O1 7 10 5 A4 O4 17
6 11 6 A1 O1 11 A5 O5
5 A2 O2 13 A2 O2 4 18
A3 O3 5 13 3 A6 O6 19
4 14 4 A3 O3 14 A7 O7
3 A4 O4 15 A4 O4 25
A5 O5 3 15 24 A8
2 16 2 A5 O5 16 A9
1 A6 O6 17 A6 O6 21
A7 O7 1 17 23 A10
23 23 A7 O7 A11
22 A8 A8 2
A9 22 A12
19 19 A9
A10 22
21 A10 OE
20 A11 27
OE 20 PGM
18 CE
CE 20
18 OE/VPP
21 1
VPP
CE VPP
2716 2732 2764

16 kbit 32 kbit 64 kbit
2 kbyte 4 kbyte 8 kbyte
PGM and VPP are used to programming

27XXX EPROM
U7
U6 12 13
U4 U5 11 A0 D0 14
10 11 10 A1 D1 15
10 11 10 11 9 A0 O0 12 9 A2 D2 17
9 A0 D0 12 9 A0 D0 12 A1 O1 A3 D3
A1 D1 A1 D1 8 13 8 18
8 13 8 13 7 A2 O2 15 7 A4 D4 19
7 A2 D2 15 7 A2 D2 15 A3 O3 A5 D5
A3 D3 A3 D3 6 16 6 20
6 16 6 16 5 A4 O4 17 5 A6 D6 21
5 A4 D4 17 5 A4 D4 17 A5 O5 A7 D7
A5 D5 A5 D5 4 18 27
4 18 4 18 3 A6 O6 19 26 A8
3 A6 D6 19 3 A6 D6 19 A7 O7 A9
A7 D7 A7 D7 25 23
25 25 24 A8 25 A10
24 A8 24 A8 A9 A11
A9 A9 21 4
21 21 23 A10 28 A12
23 A10 23 A10 A11 A13
A11 A11 2 29
2 2 26 A12 3 A14
26 A12 26 A12 A13 A15
A13 A13 27 2
27 1 A14 A16
22 A14 A15
OE 24
27 22 22 31 OE
20 PGM 20 OE OE/VPP PGM
CE CE 20 22
CE CE
1 1 28 1
VPP VPP VCC VPP
27128 27256 27512 27010

128 kbit 256 kbit 512 kbit 1024 kbit
16 kbyte 32 kbyte 64 kbyte 128 kbyte

28XX E2PROM
12 13
11 A0 D0 14
10 A1 D1 15
12 13 A2 D2
11 A0 D0 14 9 17
A1 D1 8 A3 D3 18
10 11 10 15 A4 D4
A0 D0 9 A2 D2 17 7 19
9 12 A5 D5
10 11 A1 D1 8 A3 D3 18 6 20
8 13 A4 D4 A6 D6
9 A0 I/O0 12 A2 D2 7 19 5 21
8 9 7 15 A5 D5 A7 D7
8 A1 I/O1 13 A3 D3 6 20 27
7 A0 I/O0 10 6 16 A6 D6 A8
7 A2 I/O2 15 A4 D4 5 21 26
6 A1 I/O1 11 5 17 A7 D7 A9
6 A3 I/O3 16 A5 D5 27 23
5 A2 I/O2 13 4 18 A8 A10
5 A4 I/O4 17 A6 D6 26 25
4 A3 I/O3 14 3 19 A9 A11
4 A5 I/O5 18 A7 D7 23 4
3 A4 I/O4 15 25 A12
A6 I/O6 A8 25 A10 28
A5 I/O5 3 19 24 A13
2 16 A7 I/O7 A9 4 A11 29
A6 I/O6 25 21 A14
1 17 A8 A10 28 A12 3
A7 I/O7 24 1 23 A15
23 A9 RDY/BUSY A11 29 A13 2
A8 21 2 A16
22 A10 A12 3 A14 30
A9 23 26 A17
19 A11 A13 2 A15 1
A10 2 1 A18
A12 A14 A16
20 24 24
OE 22 22 OE
21 OE OE 31 OE 31
WE 27 27 WE
18 WE WE 22 WE 22
CE 20 20 CE
CE CE CE
24 32 32
VCC 28 28 VCC
VCC VCC VCC
2816 2864 28256 28010 28040

16 kbit 64 kbit 256 kbit 1026 kbit 4096 kbit
2 kbyte 8 kbyte 32 kbyte 128 kbyte 512 kbyte

RAM (Random Access Memory)
 The uP can read the data from RAM quickly,

 The uP can write new data quickly to RAM
 RAM forgets its data if power is turned off
 Two type of is available :
 Static RAM(SRAM): ff base, fast, expensive, low
cap/vol, applied for cache , no refresh
 Dynamic RAM (DRAM): cap base, slow , low cost
high capacity/volume , applied for main memory(pc)
need refresh.

RAM(Static)
A0 D0
A1 D1
m+1 bit A2 D2 n+1 bit

Address Data
Am 2m1  (n  1)
Dn
m 1
Capacity : 2 RAM Data bus is
Bidirectional
RD : Read signal
connect to MemRD of uP
WR : Write signal
connect to MemWR of uP
CS : Chip Select CS WR RD
to Address decoder
Session 2
 Microprocessors
 History
 Data width
 8086 vs 8088
 8086 pin description
 Z80 Pin description

Microprocessors
 Microprocessors come in all kinds of varieties
from the very simple to the very complex
 Depend on data bus and register and ALU width uP
could be 4-bit , 8-bit , 16-bit, 32-bit , 64-bit
 We will discuss two sample of it
 Z80 as an 8-bit uP
 and 8086/88 as an 16-bit uP
 All uPs have
 the address bus
 the data bus
 RD, WR, CLK , RST, INT, . . .

History
Company 4 bit 8 bit 16 bit 32 bit 64 bit
8008 8088/6
4004 80386 80860
intel 8080 80186
4040 80486 pentium
8085 80286
Z8000
zilog Z80 Z8001
Z8002
6800 68006 68020
Motorola 6802 68008 68030
6809 68010 68040

Internal and External Bus
 Internal bus is a pathway for data transfer

between registers and ALU in the uPs
 External bus is available externally to
connect to RAM, ROM and I/O
 Int. and Ext. Bus width may be different
 For example
 In 8088 Int. Bus is 16-bit , Ext. bus is 8-bit
 In 8086 Int. Bus is 16-bit , Ext. bus is 16-bit

8086 vs 8088
Only external bus of 8088 is 8_bit
U? U?
33 16 33 16
MN AD0 15 MN AD0 15
22 AD1 14 22 AD1 14
19 READY AD2 13 19 READY AD2 13
CLK AD3 CLK AD3
21
RESET AD4
12
11
21
RESET AD4
12
11
8_bit Data Bus
18 AD5 10 18 AD5 10
INTR AD6 9 INTR AD6 9
AD7
AD8
8 16_bit Data Bus AD7
A8
8
7 7
AD9 6
20_bit Address
A9 6 20_bit Address
AD10 5 A10 5
AD11 4 A11 4
AD12 3 A12 3
AD13 2 A13 2
AD14 39 A14 39
AD15 38 A15 38
A16/S3 37 A16/S3 37
A17/S4 36 A17/S4 36
A18/S5 35 A18/S5 35
A19/S6 A19/S6
34 34
BHE/S7 SSO
26 26
DEN 27 DEN 27
DT/R 28 DT/R 28
30 M/IO 30 IO/M
31 HLDA 32 31 HLDA 32
17 HOLD RD 29 17 HOLD RD 29
23 NMI WR 25 23 NMI WR 25
TEST ALE 24 TEST ALE 24
INTA INTA
8088
8086MIN 8088MIN
8086
8086 Pin Assignment

8086 Pin Description
Vcc (pin 40) : Power
Gnd (pin 1 and 20) : Ground
AD0..AD7 , A8..A15 , A19/S6, A18/S5, A17/S4, A16/S3 : 20 -bit Address Bus
MN/MX’ (input) : Indicates Operating mode
READY (input , Active High) : take uP to wait state
CLK (input) : Provides basic timing for the processor
RESET (input, Active High) : At least 4 clock cycles Causes the uP immediately
terminate its present activity.
TEST’ (input , Active Low) : Connect this to HIGH
HOLD (input , Active High) : Connect this to LOW
HLDA (output , Active High) : Hold Ack
INTR (input , Active High) : Interrupt request
INTA’ (output , Active Low) : Interrupt Acknowledge
NMI (input , Active High) : Non-maskable interrupt

8086 Pin Description
DEN’ (output) : Data Enable. It is LOW when processor wants to
receive data or processor is giving out data (to 74245)
DT/R’ (output) : Data Transmit/Receive.
When High, data from uP to memory
When Low, data is from memory to uP (to74245 dir)
IO/M’ (output) : If High uP access I/O Device.
If Low uP access memory
RD’ (output) : When Low, uP is performing a read operation
WR’ (output) : When Low, uP is performing a write operation
ALE (output) : Address Latch Enable , Active High
Provided by uP to latch address
When HIGH, uP is using AD0..AD7, A19/S6,
A18/S5, A17/S4, A16/S3 as address lines

Z80 CPU Pin Assignment
27 30
M1 - A0
31
A1
19 32
MREQ - A2
20 33
System IORQ -
21 34
A3
Control Lines RD - A4
22 35
WR - A5
36
A6
28 37
RFSH - A7
38
A8 Address Bus
18 39
HALT - A9
40
A10
WAIT -
24
Z - 80 CPU 1
2
A11
CPU A12
16 3
Control Lines INT - A13
17 4
NMI - A14
5
A15
26
RESET -
14
D0
25 15
Bus BUSRQ - D1
23 12
Control Lines BUSAK - D2
8
D3
7
D4 Data Bus
6 9
 D5
11 10
+ 5V D6
29 13
GND D7

Z80 Pin Description
A15-A0 :
Address bus (output, active high, 3-state).
Used for accessing the memory and I/O ports
During the refresh cycle the I is put on this bus.
D7-D0 :
Data Bus (input/output, active high, 3-state).
Used for data exchanges with memory, I/O and
interrupts.
RD:
Read (output, active Low, 3-state) indicates that
the CPU wants to read data from memory or I/O
WR:
Write (output, active Low, 3-state) indicates
that the CPU data bus holds valid data to be
stored at the addressed memory or I/O location.

Z80 Pin Description
MREQ
Memory Request (output, active Low, 3-state).
Indicates memory read/write operation. See M1
IORQ
Input/Output Request(output,active Low,3-state)
Indicates I/O read/write operation. See M1
M1
Machine Cycle One (output, active Low).
Together with MREQ indicates opcode fetch cycle
Together with IORQ indicates an Int Ack cycle
RFSH
Refresh (output, active Low).
Together with MREQ indicates refresh cycle.
Lower 7-bits address is refresh address to DRAM

Z80 Pin Description
INT
Interrupt Request (input, active Low).
Interrupt Request is generated by I/O
devices.
Checked at the end of the current
instruction
If flip-flop (IFF) is enabled.
NMI
Non-Maskable Interrupt
(Input, negative edge-triggered).
Higher priority than INT.
Recognized at the end of the current
Instruction
Independent of the status of IFF
Forces the CPU to restart at location 0066H.

Z80 Pin Description
BUSREQ
Bus Request (input, active Low).
higher priority than NMI
recognized at the end of the current
machine cycle.
forces the CPU address bus, data
bus, and MREQ, IORQ, RD, and WR to
high-imp.
BUSACK
Bus Acknowledge (output, active,Low)
indicates to the requesting device
that address, data, and control signals
MREQ, IORQ, RD, and WR have
entered their high-impedance states.

Z80 Pin Description
RESET
Reset (input, active Low).
RESET initializes the CPU as follows:
Resets the IFF
Clears the PC and registers I and R
Sets the interrupt status to Mode 0.
During reset time, the address and data
bus go to a high-impedance state And all
control output signals go to the inactive
state.
must be active for a minimum of three full
clock cycles before the reset operation is
complete.

Z80 CPU
B
8 U
INTERNAL DATA BUS (8 BIT) F
F
E
R
DATA BUS
MUX MUX
A F
INSTRUCTION W'
TMP
Z' W Z
REGISTER
I R A' F'
B' C' B C
D' E' D E
H' L' H L ACT
DECODER
IX
IY
SP
ALU
CONTROLLER
SEQUENCER
PC
±k ±k
CONTROL
SECTION B ADDRESS BUS
16 U
INTERNAL ADDRESS BUS (16 BIT)
F
F
E
R
B CONTROL BUS
13 U
INTERNAL CONTROL BUS F
F
E
R

Z80 Programming Model

Register Set
 A : Accumulator Register
 F : Flag register
 Two sets of six general-purpose registers
 may be used individually as 8-bit A F B C D E H L (A’ F’ B’ C’
D’ E’ H’ L’)
 or in pairs as 16-bit registers AF BC DE HL (AF’ BC’ DE’ HL’)
 The Alternative registers (A’ F’ B’ C’ D’ E’ H’ L’)
not visible to the programmer but can access via:
 EXX (BC)<->(BC') , (DE)<->(DE') , (HL)<->(HL')
 EX AF, AF ’ (AF)<->(AF')
what is this instruction useful for?

Register Set(cont)
 4 16-bit registers hold memory address (pointers)
 index registers (IX) and (IY) are 16-bit memory pointers
 16 bit stack pointer (SP)
 Program counter (PC)
 Program counter (PC)

 PC points to the next opcode to be fetched from ROM
 when the µP places an address on the address bus to
fetch the byte from memory, it then increments the
program counter by one to the next location
 Special purpose registers
 I : Interrupt vector register.
 R : memory Refresh register

Flag Register
7 6 5 4 3 2 1 0
P
S Z X H X V N C
S Sign Flag (1:negativ)*
Z Zero Flag (1:Zero)
H Half Carry Flag (1: Carry from Bit 3 to Bit 4)**
P Parity Flag (1: Even)
V Overflow Flag (1:Overflow)*
N Operation Flag (1:previous Operation wassubtraction)**
C Carry Flag (1: Carry from Bit n-1 to Bit n,
with n length of operand)
*: 2-complement number representation

**: used in DAA-operation for BCD-arithmetic

DAA - Decimal Adjust Accumulator
Adjusts the content of the Accumulator A for BCD addition and subtraction
operations such as ADD, ADC, SUB, SBC, and NEG according to the table:
before DAA after DAA

Op N C Bits 4-7 H Bits 0-3 A=A+.. C
0 0 0-9 0 0-9 00 0
0 0 0-8 0 A-F 06 0
0 0 0-9 1 0-3 06 0
0 0 A-F 0 0-9 60 1
ADD
0 0 9-F 0 A-F 66 1
ADC
0 0 A-F 1 0-3 66 1
0 1 0-2 0 0-9 60 1
0 1 0-2 0 A-F 66 1
0 1 0-3 1 0-3 66 1
1 0 0-9 0 0-9 00 0
SUB
1 0 0-8 1 6-F FA 0
SBC
1 1 7-F 0 0-9 A0 1
NEG
1 1 6-F 1 6-F 9A 1

Instruction cycles, machine cycles
and “T-states”
 Instruction cycle is the time taken to complete
the execution of an instruction
 Machine cycle is defined as the time required to

complete one operation of accessing memory,
accessing IO, etc.
 T-state = 1/f (f:Z80 Clock Frequency)

 f= 4MHZ  T-state=0.25 uS

Basic CPU Timing Example

Opcode Fetch
Bus Timings (M1 Cycle)

The R register
 Is increased at every first machine cycle (M1).
 Bit 7 of it is never changed by this; only the lower
7 bits are included in the addition. So bit 7 stays
the same
 Bit 7 can be changed using the LD R,A instruction.
 LD A,R and LD R,A access the R register after it
is increased
 R is often used in programs for a random value,
which is good but of course not truly random.
 the block instructions decrease the PC with two,
so the instructions are re-executed.

Memory read/write cycle

Adding One Wait State to an M1 Cycle

Adding One Wait State to Any
Memory Cycle

IO read/write cycle
During I/O operations a single wait state is automatically inserted

Bus Request/Acknowledge Cycle

Interrupt Request/Acknowledge Cycle
Two wait states are automatically added to this cycle

Non-Maskable Interrupt Request Operation

M1 Refresh Cycle
 Takes 4T to 6Ts
 Z80 includes built in circuitry for refreshing
DRAM
 This simplifies the external interfacing
hardware
 DRAM consists of MOS transistors, which
store Information as capacitive charges; each
cell needs to be periodically refreshed
 During T3 and T4 (when Z80 is performing
internal ops), the low order address is used to
supply a 7-bit address for refresh

Wait Signal
 the Z80 samples the wait signal during T2 if

low then Z80 adds wait
 states to extend the machine cycle
 used to interface memories with slow response

time
 Slow memory is low cost

Interrupts
There are two types of interrupts:

 non mask-able (NMI)
 Could not be masked
 Jump to 0066H of memory
 mask-able(INT)
 Has 3 mode
 Can be set with the IM x Instruction
 IM 0 sets Interrupt mode 0

Interrupt Modes
 Mode 0:
 An 8 bit opcode is Fetched from Data BUS and executed
 The source interrupt device must put 8 bit opcode at data bus
 8 bit opcode usually is RST p instructions
 Mode 1:
 A jump is made to address 0038h
 No value is required at data bus
 Mode 2:
 A jump is made to address (register I × 256 + value from
interrupting device that puts at bus)
 I is high 8 bit of interrupt vector
 Value is low 8 bit of interrupt vector

Z80 CPU Instruction Description
 158 different instruction types

 Including all 78 of the 8080A CPU.
 Instruction groups
 Load and Exchange
 Block Transfer and Search
 Arithmetic and Logical
 Rotate and Shift
 Bit Manipulation (Set, Reset, Test)
 Jump, Call, and Return
 Input/Output
 Basic CPU Control

Addressing Modes
 Immediate
 Immediate Extended
 Modified Page Zero Addressing (rst p)
 Relative Addressing
 Jump Relative (2 byte)
 One Byte Op Code
 8-Bit Two’s Complement Displacement (A+2)
 Extended Addressing
 Absolute jump
 One byte opcode
 2 byte address
 Indexed Addressing
 (Index Register + Displacement) (IX+d)
 2 byte opcode
 1 byte displacement
Addressing Modes(cont.)
 Register Addressing
 LD C,B
 Implied Addressing
 Op Code implies other operand(s)
 ADD E
 Register Indirect Addressing
 16-bit CPU register pair as pointer (such as HL)
 ADD (HL)
 Bit Addressing
 set, reset, and test instructions.
 SET 3,A
 RES 7,B
Minimal Configuration of a
Z80 Microcomputer
Clock Memory Power

Generator (ROM, RAM) Supply
Address Bus
Input Out
Z - 80 CPU Data Bus Output
In
Control Bus (I/O)

Z80 Memory connection
 CPU 16 bit address bus  64 k memory(max)
 CPU 8 bit data bus  8 bit data width
 Generally should be connected
 Data to data
 Address to address
 Wr to wr
 Rd to rd
 Mreq to cs

Memory connection (cont.)
 If only one RAM chip Full size (64 kb capacity)
D7~D0 D7~D0
RAM
64 kb
A15~A0 A15~A0
RD WR CS
Z80
CPU
RD
WR
MREQ

 If RAM capacity was 32 kb
 A15 composed with MREQ
 RAM area is from 0000h to 7FFFh
D7~D0 D7~D0
RAM
32 kb
A14~A0 A14~A0
RD WR CS
Z80
CPU
RD
WR
A15 MREQ

 There is two 32 kb RAM
 Problem: Bus Conflict. The two memory
chips will provide data at the same time
when microprocessor performs a memory
read.
 Solution: Use address line A15 as an
“arbiter”. If A15 outputs a logic “1” the
upper memory is enabled (and the lower
memory is disabled) and vice-versa.

 There is two 32 kb RAM
 A15 applied to select one RAM chip
 Two RAM area is from 0000h to 7FFFh (RAM1)
and 8000h to FFFFh (RAM1)
D7~D0 D7~D0 D7~D0

RAM RAM
32 kb 32 kb
A14~A0 A14~A0 A14~A0
RD WR CS RD WR CS
Z80
CPU
RD
WR
A15 MREQ

 32 kb ROM and 32 kb RAM
 ROM doesn’t have wr signal
D7~D0 D7~D0 D7~D0

ROM RAM
32 kb 32 kb
A14~A0 A14~A0 A14~A0
OE CS RD WR CS
Z80
CPU
RD
WR
A15 MREQ

There is 4 memory chip
A14 and A15 applied to chip selection
D7~D0 D7~D0 D7~D0 D7~D0 D7~D0

ROM RAM RAM RAM
16 kb 16 kb 16 kb 16 kb
Z80
A13~A0 A13~A0 A13~A0 A13~A0 A13~A0
CPU OE CS RD WR CS RD WR CS RD WR CS
RD
WR
A15
A14
MREQ En
S0
S1

Address Bit Map
Selects chip Selects location within chips
A15 to A0 AA AA AAAA AAAA AAAA

Memory
(HEX) 11 11 1198 7654 3210
Chip
54 32 10
0000h 00 00 0000 0000 0000
ROM
3FFFh 00 11 1111 1111 1111
4000h 01 00 0000 0000 0000
RAM1
7FFFh 01 11 1111 1111 1111
8000h 10 00 0000 0000 0000
RAM2
BFFFh 10 11 1111 1111 1111
C000h 11 00 0000 0000 0000
RAM3
FFFFh 11 11 1111 1111 1111

Memory Map
 Represents the memory type 0000h
ROM
 Address area of each memory chip 16k
3FFFh
 Empty area 4000h
RAM1
7FFFh 16k
D7~D0 D7~D0 D7~D0 D7~D0 D7~D0
ROM
16 kb
RAM
16 kb
RAM
16 kb
RAM
16 kb
8000h
A13~A0 A13~A0 A13~A0
WR CS
A13~A0
WR CS
A13~A0
WR CS
RAM2
OE CS RD RD RD
BFFFh 16k
RD
C000h
WR
RAM3
A15
A14
En
MREQ
S0
S1
FFFFh 16k

Memory Map
 Empty Area cann’t write and read 0000h
 Read op. returns FFh value (usualy) ROM
 Write op. cann’t store any value on it 3FFFh
4000h
Empty
D7~D0 D7~D0 D7~D0 D7~D0

7FFFh
ROM
16 kb
RAM
16 kb
RAM
16 kb
8000h
RAM2
A13~A0 A13~A0 A13~A0 A13~A0
OE CS RD WR CS RD WR CS
RD
BFFFh
C000h
WR
RAM3
A15
A14
En
MREQ
S0
S1
FFFFh

Memory Map
 Empty Area cann’t write and read 0000h
 Read op. returns FFh value (usualy) ROM
 Write op. cann’t store any value on it 3FFFh
4000h
Empty
D7~D0 D7~D0 D7~D0

7FFFh
ROM
16 kb
RAM
16 kb
8000h
RAM
A13~A0 A13~A0 A13~A0
OE CS RD WR CS
RD
BFFFh
C000h
WR
A15
A14
En
MREQ
S0 Empty
S1
FFFFh

Full and Partial Decoding
 Full (exhaust) Decoding

 All of the address lines are connected to any memory/device
to perform selection
 Absolute address : any memory location has one address
 Partial Decoding
 When some of the address lines are connected the
memory/device to perform selection
 Using this type of decoding results into roll-over addresses
(fold back or shading).
 roll-over address : any memory location has more than one
address

Partial Decoding
 A15~A12 has no connection
 Then doesn’t play any role in addressing
 What is the Memory and Address Bit map?
D7~D0 D7~D0
RAM
4 kb
A11~A0 A11~A0
A15~A12 X RD WR CS
Z80 RD
CPU WR
MREQ

Partial Decoding 0000h
RAM
0FFFh
1000h
 Every memory location has more than one address 1FFFh
RAM’
 For example first RAM location has addresses: 2000h
RAM’
0000h 2FFFh
3000h
1000h RAM’
3FFFh
2000h
3000h Roll-over Address
……………. F000h
……………. RAM’
FFFFh
F000h
D7~D0 D7~D0
RAM
AAAA AAAA AAAA AAAA 4 kb
A15 to A0 Memory A11~A0 A11~A0
1111 1198 7654 3210
(HEX) Chip A15~A12 X RD WR CS
5432 10
X000h xxxx 0000 0000 0000 Z80 RD
RAM CPU WR
XFFFh xxxx 1111 1111 1111 MREQ

Partial Decoding
 A12 only connected to RAM
 A13 has no connection
 What is the memory map?
D7~D0 D7~D0 D7~D0

ROM RAM
4 kb 8 kb
A12~A0 A11~A0 A12~A0
X OE
A13 CS RD WR CS
Z80 RD
CPU WR
A15
A14
MREQ

Partial Decoding
 8 roll-over address for ROM
 4 roll-over address for RAM
AAAA AAAA AAAA AAAA

D7~D0 D7~D0 D7~D0 Memory
ROM RAM
1111 1198 7654 3210
Chip
4 kb 8 kb 5432 10
A12~A0 A11~A0 A12~A0
0xxx 0000 0000 0000

X
OE CS RD WR CS
Z80 A13 ROM
CPU 0xxx 1111 1111 1111
RD
WR
X0x0 0000 0000 0000
RAM
A15
A14
MREQ
X0x1 1111 1111 1111

Partial Decoding
0000h 0000h
ROM
0FFFh
RAM’
Conflict
1000h
ROM’
1FFFh 1FFFh
D7~D0 D7~D0 D7~D0

ROM
2000h 2000h
ROM’
RAM 2FFFh
4 kb 8 kb RAM’
A12~A0 A11~A0 A12~A0 3000h
ROM’
3FFFh 3FFFh
X
OE CS RD WR CS
Z80 A13 4000h 4000h
ROM’
CPU 4FFFh
ROM’
RD 5000h
WR
5FFFh 5FFFh
6000h 6000h
ROM’
A15
A14
MREQ
6FFFh
7000h
ROM’
7FFFh 7FFFh
8000h F000h
AAAA AAAA AAAA AAAA
Memory RAM
1111 1198 7654 3210
Chip
5432 10 9FFFh
A000h
0xxx 0000 0000 0000 4k
ROM RAM’
0xxx 1111 1111 1111 BFFFh
8k C000h
X0x0 0000 0000 0000
RAM
X0x1 1111 1111 1111 DFFFh
E000h

Partial Decoding
0000h 0000h
ROM
0FFFh
1000h
ROM’
1FFFh 1FFFh
D7~D0 D7~D0 D7~D0

ROM
2000h 2000h
ROM’
RAM 2FFFh
4 kb 8 kb
A12~A0 A11~A0 A12~A0 3000h
ROM’
3FFFh 3FFFh
X
OE CS RD WR CS
Z80 A13 4000h 4000h
ROM’
CPU
RD
WR
Conflict
RAM’ 4FFFh
5000h
ROM’
5FFFh 5FFFh
6000h 6000h
ROM’
A15
A14
MREQ
6FFFh
RAM’
7000h
ROM’
7FFFh 7FFFh
8000h F000h
AAAA AAAA AAAA AAAA
Memory
1111 1198 7654 3210
Chip
5432 10 9FFFh
A000h
0xxx 0000 0000 0000 4k
ROM
0xxx 1111 1111 1111 BFFFh
8k C000h
X1x0 0000 0000 0000
RAM RAM
X1x1 1111 1111 1111 DFFFh
E000h
hsabaghianb @ kashanu.ac.ir RAM’ Microprocessors 1-90

Full (exhaustive) decoding
AAAA AAAA AAAA AAAA
Memory
1111 1198 7654 3210
Chip
5432 10 A12~A0 A12~A0
0000 0000 0000 0000 D7~D0
ROM 2764
0001 1111 1111 1111 EPROM
0010 0000 0000 0000 8k8
RAM
OE CE
0010 0111 1111 1111
D7~D0
RD
A13 C 0000h-07FFh
Y0
A12 B Y1 0800h-0FFFh
A11 A Y2 1000h-17FFh 7421
1800h-1FFFh A10~A0 A10~A0
74138 Y3 D7~D0
2000h-27FFh 6116
Y4 RWM
A15 G2A Y5 2k8
A14 G2B Y6 RD WR CS
MREQ G1 Y7
RD WR

Partial decoding
AAAA AAAA AAAA AAAA
Memory
1111 1198 7654 3210
Chip
5432 10 A12~A0 A12~A0
0000 0000 0000 0000 D7~D0
ROM 2764
0001 1111 1111 1111 EPROM
001x x000 0000 0000 8k8
RAM
OE CE
001x x111 1111 1111
D7~D0
RD
A15 C 0000h-1FFFh
Y0
A14 B Y1 2000h-3FFFh
A13 A Y2
A10~A0 A10~A0
74138 Y3 D7~D0
6116
Y4 RWM
MREQ G2A Y5 2k8
GND G2B Y6 RD WR CS
VCC G1 Y7
RD WR

1 Bit Memory With Separated I/O
D7-D0
D7 D1 D0
Din Din Din

A11~A0 Dout A11~A0 Dout A11~A0 Dout
A11-A0 A11-A0 A11-A0
2147 2147 2147
RWM RWM RWM
4k1 4k1 4k1
WR / RD CS WR / RD CS WR / RD CS
WR / RD
CS

What is the memory(addr. bit) map
A12~A0
D7~D0
2764
EPROM
8k8
OE CE
RD
A15 C 0000h-1FFFh
Y0
A14 B Y1
2000h-3FFFh D7-D0
D7 D1 D0
A13 A Y2
74138 Y3 Din Din Din

A11~A0 Dout A11~A0 Dout A11~A0 Dout
Y4 A11-A0 A11-A0 A11-A0
2147 2147 2147
MREQ G2A Y5 RWM RWM RWM
4k1 4k1 4k1
GND G2B Y6 WR / RD CS WR / RD CS WR / RD CS
VCC G1 Y7
WR WR
RD

Adding RAM & ROM

Minimum Z80 Computer
System

Z80-µP-Family (Typical Environment)
PIO DMA
+5V
INT - INT - IEI RDY
System Buses (Address, Data, Control)
INT - INT - INT - IEO W/RDYB -

Z80 CPU CTC SIO
+5V IEI IEO IEI TxCA - TxCB -
ZC/TO1 ZC/TO2 RxCA - RxCB -

Z80 Input Output
 Z80 at most could have 256 input port and 256 output
 8 bit port address is placed on A7–A0 pin to select the
I/O device
 OUT (n), A
 n is 8 bit port address
 Content of A is data
 OUT (C), r
 Content of C is a port address
 r is a data register
 IN A, (n)
 n is 8 bit port address
 Data is transfered to A
 IN r (C)
 Content of Reg C is a port address
 Input
hsabaghianb data is
@ kashanu.ac.ir transfered to r (data reg) Microprocessors 1-98
Remember IO read/write cycle

Z80 and simple output port
A15
OUT (03), A
A14
:
A0
D7 D0 Q0
D6 D1 Q1
D5 D2 Q2
Z80 D4 D3 Q3
D3 D4 Q4
74LS373
CPU D2 D5 Q5
D1 D6 Q6
D0 D7 Q7
LE OE
IORQ
WR
A AA A AAA A
IOWR 7 65 4 321 0

Z80 and simple input port
A15 5V
A14 IN A, (02)
:
A0
D7 Y0 A0
D6 Y1 A1
D5 Y2 A2
Z80 D4 Y3 A3
D3 Y4 74LS244 A4
CPU D2 Y5 A5
D1 Y6 A6
D0 Y7 A7
G1 G2
IORQ
RD
AA AA A AAA
IORD 76 54 3 210

8088 and simple output port
A19
A18
:
A0
D7 D0 Q0
D6 D1 Q1
D5 D2 Q2
D4 D3 Q3
D3 D4 Q4
74LS373
D2 D5 Q5
8088 D1 D6 Q6
Minimum D0 D7 Q7
Mode
LE OE
IOR
IOW
AAAAAAAAAAAAAAAAIOW
1 1 11 11 9 8 7 654 3 21 0
5 4 32 10

8088 and simple input port
A19 5V
A18
:
A0
What is this? D7 Y0 A0
D6 Y1 A1
D5 Y2 A2
D4 Y3 A3
D3 Y4 74LS244 A4
D2 Y5 A5
8088 D1 Y6 A6
Minimum D0 Y7 A7
Mode
G1 G2
IOR
IOW
AAAAAAAAAAAAAAAAIOW
1 1 11 11 9 8 76 5 4 3 21 0
5 4 32 10

Simplified Drawing of 8088 Minimum Mode
D7-D0
A7 - A0 B7 - B0
DEN E
DT / R DIR 74LS245
A7-A0
AD7 - AD0 D7 - D0 Q7 - Q0
GND OE
LE 74LS373
A15-A8
A15 - A8 D7 - D0 Q7 - Q0
GND OE
8088 LE 74LS373
A19/S6 - A16/ A19-A16
S3 D7 - D4 Q7 - Q4
D3 - D0 Q3 - Q0
GND OE
ALE LE 74LS373
RD MEMR
IO / M
MEMW
WR
IOR
IOW

Minimum Mode
220 bytes or 1MB memory
D7 - D0 D7 - D0
A19 - A0 A19 - A0
Simplified
Drawing of
1 MB
8088 Minimum
Memory
Mode
MEMR RD
MEMW WR
CS

What are the memory locations of a
1MB (220 bytes) Memory?
A19 to AAAA AAAA AAAA AAAA AAAA

A0 1111 1111 1198 7654 3210
(HEX) 9876 5432 10
00000 0000 0000 0000 0000 0000
FFFFF 1111 1111 1111 1111 1111
Example: 34FD0
0011 0100 11111 1101 0000

Minimum Mode
512 kB memory
D7 - D0 D7 - D0
What do we do with A19?
A19
A18 - A0 A18 - A0
1) Don’t connect it
Simplified 2) Connect to cs
Drawing of
512 kB
8088 MinimumWhat is the difference?
Memory
Mode
MEMR RD
MEMW WR
CS

512 kB Memory Map
 Don’t connect it 00000h
512k
 A19 is not connected to 7FFFFh Mem
the memory so even if
the 8088 microprocessor
outputs a logic “1”,the 80000h
512k
memory cannot “see” it. FFFFFh Mem’
 A19=0 is the same as
A19=1 for Memory
 Connect to cs 00000h
512k
 If A19=0 Memory chip 7FFFFh Mem
act normal fanction
80000h
FFFFFh Empty

2  512 kB memory
D7 - D0 D7 - D0
A19
512 kB
RAM1
A18 - A0 A18 - A0
MEMR
MEMR RD
WR CS
MEMW MEMW
D7 - D0
512 kB
Simplified
RAM2
Drawing of A18 - A0
8088 Minimum
MEMR
Mode RD
WR CS
MEMW

2  512 kB memory
What are the memory locations of 00000h

two consecutive 512KB (219 bytes)
Memory? 512k
RAM1
AAAA AAAA AAAA AAAA AAAA

Memory
1111 1111 1198 7654 3210
Chip
9876 5432 10 7FFFFh
0000 0000 0000 0000 0000 80000h
0111 1111 1111 1111 1111

ROM
512k
1000 0000 0000 0000 0000
RAM2
1111 1111 1111 1111 1111
RAM
FFFFFh

Interfacing four 256K Memory A17
:
Chips to A0
D7
256KB
the 8088 Microprocessor
:
D0 #4
RD
WR
A19
CS
A18
A17 A17
: :
A0 A0
D7 D7
256KB
: :
D0 D0 #3
MEMR RD
MEMW WR
8088 CS
Minimum
A17
Mode :
A0
D7
256KB
:
D0 #2
RD
WR
CS
A17
:
A0
D7
256KB
:
D0 #1
RD
WR
CS

Interfacing four 256K Memory A17
:
A0
Chips to D7
:
256KB
#4
the 8088 Microprocessor D0
RD
WR
A19
CS
A18
A17 A17
: :
A0 A0
D7 D7
256KB
: :
D0 D0 #3
MEMR RD
MEMW WR
8088 CS
Minimum
A17
Mode :
A0
D7
256KB
:
D0 #2
RD
WR
CS
A17
:
A0
D7
256KB
:
D0 #1
RD
WR
CS

Memory chip#__ is mapped to:

1111 1111 1198 7654 3210 Memory
9876 5432 10 Chip
RAM#1
RAM#2
RAM#3
RAM#4

A12
:
A0
A19 D7
8KB
Interfacing A18
A17
:
D0 #?
several 8K
A16 RD
A15 WR
A14
Memory
CS
A13
A12
Chips to the
:
:
A0
8088 P
D7
:
:
D0
MEMR
MEMW
8088
Minimum
Mode
A12
:
A0
D7
8KB
:
D0 #2
RD
WR
CS
A12
:
A0
D7
:
8KB
D0 #1
RD
WR
CS

A12
Interfacing
:
A0
A19 D7
128
8KB
A18 :
A17 D0 #128
8K Memory
A16 RD
A15 WR
Chips to the
A14
CS
A13
8088 P
A12
:
:
A0
D7
:
:
D0
MEMR
MEMW
8088
Minimum
Mode
A12
:
A0
D7
8KB
:
D0 #2
RD
WR
CS
A12
:
A0
D7
:
8KB
D0 #1
RD
WR
CS

A12
:
A0
A19 D7
8KB
A18 :
A17 D0 #128
A16 RD
A15 WR
Interfacing
A14
CS
A13
128
A12
:
:
A0
8K Memory D7
:
Chips to the :
D0
MEMR
MEMW
8088 P
8088
Minimum
Mode
A12
:
A0
D7
8KB
:
D0 #2
RD
WR
CS
A12
:
A0
D7
8KB
:
D0 #1
RD
WR
CS

Memory chip#__ is mapped to:
1111 1111 1198 7654 3210 Memory
9876 5432 10 Chip
RAM#1
RAM#2
RAM#126
RAM#127
RAM#128

What is the Memory and Address Bit map?
A12~A0 A12~A0
D7~D0
2764
EPROM
8k8
OE CE D7~D0
7408 RD
A14 C Y0
A13 B Y1
A12 A Y2
A10~A0 A10~A0
74138 Y3 D7~D0
6116 74244 input
Y4 RWM G1G 2
MREQ G2A Y5 2k8
A15 G2B Y6 RD WR CS
VCC G1 Y7
RD WR

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‫ريزپردازنده ها‬

hsabaghianb @ kashanu.ac.ir Microprocessors 1-1

hsabaghianb @ kashanu.ac.ir Microprocessors 1-2

hsabaghianb @ kashanu.ac.ir Microprocessors 1-3

hsabaghianb @ kashanu.ac.ir Microprocessors 1-4

hsabaghianb @ kashanu.ac.ir Microprocessors 1-5

hsabaghianb @ kashanu.ac.ir Microprocessors 1-6

hsabaghianb @ kashanu.ac.ir Microprocessors 1-7

hsabaghianb @ kashanu.ac.ir Microprocessors 1-8

hsabaghianb @ kashanu.ac.ir Microprocessors 1-9

hsabaghianb @ kashanu.ac.ir Microprocessors 1-10

 Logic circuit provides limited function for one

hsabaghianb @ kashanu.ac.ir Microprocessors 1-11

hsabaghianb @ kashanu.ac.ir Microprocessors 1-12

 The uP is the ‘brain of the microcomputer’

hsabaghianb @ kashanu.ac.ir Microprocessors 1-13

 microprocessor (MPU) typically contains

hsabaghianb @ kashanu.ac.ir Microprocessors 1-14

 MPU is the brain of microcomputer

hsabaghianb @ kashanu.ac.ir Microprocessors 1-15

hsabaghianb @ kashanu.ac.ir Microprocessors 1-16

 I/O is the link between the MPU and the outside

 An input port is a circuit through which an

 An output port is a circuit that allows the MPU to

 I/O ports connect both digital and analogue

hsabaghianb @ kashanu.ac.ir Microprocessors 1-17

 The individual subsystems of the digital computer are

hsabaghianb @ kashanu.ac.ir Microprocessors 1-18

There are three main bus groups

hsabaghianb @ kashanu.ac.ir Microprocessors 1-19

 Examples of data transfers

 These are called read and write operations

hsabaghianb @ kashanu.ac.ir Microprocessors 1-20

 The Address Bus is used to transmit the address

 The Address Bus is unidirectional ( one way ):

hsabaghianb @ kashanu.ac.ir Microprocessors 1-21

 Control signals are unidirectional, and are mainly

 Example Control signals

hsabaghianb @ kashanu.ac.ir Microprocessors 1-22

hsabaghianb @ kashanu.ac.ir Microprocessors 1-23

 uP can read instructions from ROM quickly

hsabaghianb @ kashanu.ac.ir Microprocessors 1-24

 Masked ROM or just ROM

hsabaghianb @ kashanu.ac.ir Microprocessors 1-25

m+1 bit A2 D2 n+1 bit

CE (CS ) : Chip Enable

hsabaghianb @ kashanu.ac.ir Microprocessors 1-26

OE falls to data valid

hsabaghianb @ kashanu.ac.ir Microprocessors 1-27

2716 2732 2764

PGM and VPP are used to programming

hsabaghianb @ kashanu.ac.ir Microprocessors 1-28

27128 27256 27512 27010

hsabaghianb @ kashanu.ac.ir Microprocessors 1-29

2816 2864 28256 28010 28040

hsabaghianb @ kashanu.ac.ir Microprocessors 1-30

 The uP can read the data from RAM quickly,

hsabaghianb @ kashanu.ac.ir Microprocessors 1-31

m+1 bit A2 D2 n+1 bit

hsabaghianb @ kashanu.ac.ir Microprocessors 1-33

hsabaghianb @ kashanu.ac.ir Microprocessors 1-34

Company 4 bit 8 bit 16 bit 32 bit 64 bit