Chapter 11

Operational AmpliIiers and Applications

Chapter Goals
Understand the 'magic oI negative Ieedback and the
characteristics oI ideal op amps.
Understand the conditions Ior non-ideal op amp behavior so
they can be avoided in circuit design.
Demonstrate circuit analysis techniques Ior ideal op amps.
Characterize inverting, non-inverting, summing and
instrumentation ampliIiers, voltage Iollower and Iirst order
Iilters.
Learn the Iactors involved in circuit design using op amps.
Find the gain characteristics oI cascaded ampliIiers.
Special Applications: The inverted ladder DAC and successive
approximation ADC
DiIIerential AmpliIier Model: Basic
Represented by:
A open-circuit voltage gain
v
id
(v

-v
-
) diIIerential input signal
voltage
R
id
ampliIier input resistance
R
o
ampliIier output resistance
The signal developed at the ampliIier
output is in phase with the voltage applied
at the input (non-inverting) terminal and
180 out oI phase with that applied at the
- input (inverting) terminal.
LM741 Operational AmpliIier: Circuit
Architecture
Current Mirrors
deal Operational AmpliIier
The 'ideal op amp is a special case oI the ideal diIIerential ampliIier
with inIinite gain, inIinite R
id
and zero R
o
.
and
I A is inIinite, v
id
is zero Ior any Iinite output voltage.
nIinite input resistance R
id
Iorces input currents i

and i
-
to be zero.
The ideal op amp operates with the Iollowing assumptions:
t has inIinite common-mode reiection, power supply reiection, open-
loop bandwidth, output voltage range, output current capability and
slew rate
t also has zero output resistance, input-bias currents, input-oIIset
current, and input-oIIset voltage.
A
o
v
id
v =
0
id
v
lim
=
A
The nverting AmpliIier: ConIiguration
The positive input is grounded.
A 'Ieedback network composed oI resistors R
1
and R
2
is connected
between the inverting input, signal source and ampliIier output node,
respectively.
nverting AmpliIier:Voltage Gain
The negative voltage gain
implies that there is a 180
0
phase
shiIt between both dc and
sinusoidal input and output
signals.
The gain magnitude can be
greater than 1 iI R
2
~ R
1
The gain magnitude can be less
than 1 iI R
1
~ R
2
The inverting input oI the op
amp is at ground potential
(although it is not connected
directly to ground) and is said to
be at ;irtual ground.
0
o
v
2 2
i
1
i
s
v = R R
s
1
s
v
s
i
R
=
But i
s
i
2
and v
-
0 (since v
id
v

- v
-
0)
and
1
2
s
v
o
v
R
R
v
A = =
nverting AmpliIier: nput and Output
Resistances


R
in
=
v
s
i
s
=R
1
since v

=0
R
out
is Iound by applying a test current
(or voltage) source to the ampliIier
output and determining the voltage (or
current) aIter turning oII all
independent sources. Hence, v
s
0
1 1
i
2 2
i
x
v R R =
But i
1
i
2
)
1 2
(
1
i
x
v R R =
Since v
-
0, i
1
0. ThereIore v
x
0
irrespective oI the value oI i
x
.
0 =
out
R
nverting AmpliIier: Example
!roblem: Design an inverting ampliIier
Gi;en Data: A
v
20 dB, R
in
20k,
ssumptions: deal op amp
nalysis: nput resistance is controlled by R
1
and voltage gain is set
by R
2
/ R
1
.
and A
v
-100
A minus sign is added since the ampliIier is inverting.


A
v
dB

'

+
'
=20log
10
A
v

'

+
'

, A
v
=10
40dB/20dB
=100
= = k 20
1 in
R R

A
v
=
R
2
R
1
R
2
=100R
1
=2M
The Non-inverting AmpliIier: ConIiguration
The input signal is applied to the non-inverting input terminal.
A portion oI the output signal is Ied back to the negative input
terminal.
Analysis is done by relating the voltage at v
1
to input voltage v
s
and
output voltage v
o
.
Non-inverting AmpliIier: Voltage Gain,
nput Resistance and Output Resistance
Since i
-
0 and
But v
id
0
Since i

0
2 1
1
o
v
1
v
R R
R

=
1
v
id
v
s
v =
1
v
s
v =
1
2
1
1
2 1
s
v
o
v
1
2 1
s
v
o
v
R
R
R
R R
v
A
R
R R
=

= =

=
=

=
i
s
v
in
R
R
out
is Iound by applying a test current source to the ampliIier output
aIter setting v
s
0. t is identical to the output resistance oI the inverting
ampliIier i.e. R
out
0.
Non-inverting AmpliIier: Example
!roblem: Determine the output voltage and current Ior the given non-
inverting ampliIier.
Gi;en Data: R
1
3k, R
2
43k, v
s
0.1 V
ssumptions: deal op amp
nalysis:
Since i
-
0,


A
v
=1
R
2
R
1
=1
43k
3k
=15.3
v
o
= A
v
v
s
=(15.3)(0.1V)=1.53V
A 3 . 33
k 3 k 43
V 53 . 1
1 2
o
v
o
i u =

=

=
R R
Finite Open-loop Gain and Gain Error
2 1
1
o
v
o
v
2 1
1
1
v
R R
R
R R
R

=
=

=
0
0
is called the
1eedback 1actor.
0
0
A
A
v
A
A A A

= =
= = =
1
s
v
o
v
)
o
v
s
v ( )
1
v
s
v (
id
v
o
v
A0 is called loop gain.
For A0 ~~1,


A
v

1
0
=1
R
2
R
1
This is the 'ideal voltage gain oI
the ampliIier. I A0 is not ~~1,
there will be 'Gain Error.
Gain Error
Gain Error is given by
GE (ideal gain) - (actual gain)
For the non-inverting ampliIier,
Gain error is also expressed as a Iractional or percentage
error.
) 1 (
1
1
1
0 0 0 0 A A
A
GE

=


FGE=
1
0

A
1A0
1
0
=
1
1A0

1
A0
PGE
1
A0
-100
Gain Error: Example
!roblem: Find ideal and actual gain and gain error in percent
Gi;en data: Closed-loop gain oI 100,000, open-loop gain oI
1,000,000.
pproach: The ampliIier is designed to give ideal gain and deviations
Irom the ideal case have to be determined. Hence,
.
Note. R
1
and R
2
aren`t designed to compensate Ior the Iinite open-loop
gain oI the ampliIier.
nalysis:


0=
1
10
5


A
v
=
A
1A0
=
10
6
1
10
6
10
5
=9.09x10
4
PGE=
10
5
9.09x10
4
10
5
-100=9.09
Output Voltage and Current Limits
Practical op amps have limited
output voltage and current ranges.
Voltage: Usually limited to a Iew
volts less than power supply span.
Current: Limited by additional
circuits (to limit power dissipation
or protect against accidental short
circuits).
The current limit is Irequently
speciIied in terms oI the minimum
load resistance that the ampliIier
can drive with a given output
voltage swing. Eg:


i
o
=
5V
500
=10mA
)
2 1
(
o
v
1 2
o
v
o
v
F
i
L
i
o
i
R R
L
R
EQ
R
EQ
R R R
L
R
=
=

= =
For the inverting ampliIier,
2
R
L
R
EQ
R =
Example PSpice Simulations oI
Non-inverting AmpliIier Circuits
The Unity-gain AmpliIier or 'BuIIer
This is a special case oI the non-inverting ampliIier, which is also
called a voltage Iollower, with inIinite R
1
and zero R
2
. Hence A
v
1.
t provides an excellent impedance-level transIormation while
maintaining the signal voltage level.
The 'ideal buIIer does not require any input current and can drive any
desired load resistance without loss oI signal voltage.
Such a buIIer is used in many sensor and data acquisition system
applications.
The Summing AmpliIier
Scale Iactors Ior the 2 inputs
can be independently adiusted
by the proper choice oI R
2
and
R
1
.
Any number oI inputs can be
connected to a summing
iunction through extra
resistors.
This circuit can be used as a
simple digital-to-analog
converter. This will be
illustrated in more detail, later.
1
1
v
1
i
R
=
2
2
v
2
i
R
=
3
o
v
3
i
R
=
Since the negative ampliIier
input is at virtual ground,
Since i
-
0, i
3
i
1
i
2
.


v
o
=
R
3
R
1
v
1

R
3
R
2
v
2
The DiIIerence AmpliIier
This circuit is also called a
diIIerential ampliIier, since it
ampliIies the diIIerence between
the input signals.
R
in2
is series combination oI R
1
and R
2
because i

is zero.
For v
2
0, R
in1
R
1
. as the circuit
reduces to an inverting ampliIier.
For general case, i
1
is a Iunction
oI both v
1
and v
2
.
1
v
1
2
-
v
1
2 1
)
-
v
1
v (
1
2
-
v
2 1
i
-
v
2 2
i
-
v
o
v
R
R
R
R R
R
R
R R

=
= =

'
+

'

=


v

=
R
2
R
1
R
2
v
2
Also,
Since v
-
v

)
2
v
1
(v
1
2
v =
R
R
o
For R
2
R
1
)
2
v
1
(v v =
o
DiIIerence AmpliIier: Example
!roblem: Determine v
o
Gi;en Data: R
1
10k, R
2
100k, v
1
5 V, v
2
3 V
ssumptions: deal op amp. Hence, v
-
v

and i
-
i

0.
nalysis: Using dc values,


A
dm
=
R
2
R
1
=
100k
10k
=10
J
o
= A
dm
J
1
J
2

'


+
'


=10(53)
J
o
=20.0 V
Here A
dm
is called the 'diIIerential mode voltage gain oI the diIIerence ampliIier.
Finite Common-Mode Reiection Ratio
(CMRR)
A(or A
dm
) diIIerential-mode gain
A
cm
common-mode gain
v
id
diIIerential-mode input voltage
v
ic
common-mode input voltage
A real ampliIier responds to signal
common to both inputs, called the
common-mode input voltage (v
ic
).
n general,


v
o
= A
dm
v
id

A
cm
v
ic
A
dm

'




+
'




= A
dm
v
id

v
ic
CMRR

'



+
'



CMRR=
A
dm
A
cm

and CMRR(dB)=20log
10
(CMRR)
An ideal ampliIier has A
cm
0, but Ior a
real ampliIier,
2
1
id
v
ic
v v =
2
2
id
v
ic
v v =

v
o
= A
dm
(v
1
v
2
)A
cm
v
1
v
2
2

'



+
'



v
o
= A
dm
(v
id
)A
cm
(v
ic
)
Finite Common-Mode Reiection Ratio:
Example
!roblem: Find output voltage error introduced by Iinite CMRR.
Gi;en Data: A
dm
2500, CMRR 80 dB, v
1
5.001 V, v
2
4.999 V
ssumptions: Op amp is ideal, except Ior CMRR. Here, a CMRR in dB
oI 80 dB corresponds to a CMRR oI 10
4
.
nalysis:
The output error introduced by Iinite CMRR is 25 oI the expected ideal
output.


v
id
=5.001V4.999V
v
ic
=
5.001V4.999V
2
=5.000V
v
o
= A
dm
v
id

v
ic
CMRR

'


+
'


=2500 0.002
5.000
10
4

'


+
'


V=6.25V
n the "ideal" case, v
o
= A
dm
v
id
=5.00 V


output error=
6.255.00
5.00
-100=25
uA741 CMRR Test: DiIIerential Gain
DiIIerential Gain A
dm
5 V/5 mV 1000
uA741 CMRR Test: Common Mode Gain
Common Mode Gain A
cm
160 mV/5 V .032
CMRR Calculation Ior uA741

CMRR =
A
dm
A
cm
=
1000
.032
= 3.125x10
4
CMRR(dB) = 20log
10
CMRR
)
= 89.9 dB
nstrumentation AmpliIier
Combines 2 non-inverting ampliIiers
with the diIIerence ampliIier to
provide higher gain and higher input
resistance.
)
b
v
a
(v
3
4
v =
R
R
o
b
v
2
i )
1
i(2
2
i
a
v = R R R
1
2
2
v
1
v
i
R

=
)
2
v
1
(v
1
2
1
3
4
v =

'
+

'

R
R
R
R
o
deal input resistance is inIinite
because input current to both op
amps is zero. The CMRR is
determined only by Op Amp 3.
%
nstrumentation AmpliIier: Example
!roblem: Determine J
o
Gi;en Data: R
1
15 k, R
2
150 k, R
3
15 k R
4
30 k J
1
2.5 V,
J
2
2.25 V
ssumptions: deal op amp. Hence, v
-
v

and i
-
i

0.
nalysis: Using dc values,


A
dm
=
R
4
R
3
1
R
2
R
1

'




+
'




=
30k
15k
1
150k
15k

'


+
'


=22
J
o
= A
dm
(J
1
J
2
)=22(2.52.25)=5.50V
The Active Low-pass Filter
Use a phasor approach to gain analysis oI
this inverting ampliIier. Let s i.


A
v
=
v
o
( i)
v ( i)
=
Z
2
( i
Z
1
( i


Z
1
i
)
= R
1


Z
2
( i)=
R
2
1
i
R
2

1
i
=
R
2
iR
2
1


A
v
=
R
2
R
1
1
(1 iR
2
)
=
R
2
R
1
e
i6
(1
i

c
)

c
=261
c
=
1
R
2

1
c
=
1
26R
2

1
c
is called the high Irequency 'cutoII oI
the low-pass Iilter.
Active Low-pass Filter (continued)
At Irequencies below 1
c
(1

in the
Iigure), the ampliIier is an
inverting ampliIier with gain set
by the ratio oI resistors R
2
and
R
1
.
At Irequencies above 1
c
, the
ampliIier response 'rolls oII at
-20dB/decade.
Notice that cutoII Irequency and
gain can be independently set.

A
v
=
R
2
R
1
e
i6
(1
i

c
)

'







+
'







=
R
2
R
1
1
2

c

'




+
'




2
e
i6
e
itan
1
(/
c
)

'






+
'






=
R
2
R
1
1

c

'




+
'




2
e
i|6 tan
1
(/
c
)|
magnitude phase
Active Low-pass Filter: Example
!roblem: Design an active low-pass Iilter
Gi;en Data: A
v
40 dB, R
in
5 k, 1

2 kHz
ssumptions: deal op amp, speciIied gain represents the desired low-
Irequency gain.
nalysis:
nput resistance is controlled by R
1
and voltage gain is set by R
2
/ R
1
.
The cutoII Irequency is then set by C.
The closest standard capacitor value oI 160 pF lowers cutoII Irequency
to 1.99 kHz.
100
dB 20 / dB 40
10 = =
v
A
= = k 5
1 in
R R


A
v
=
R
2
R
1
R
2
=100R
1
=500k


=
1
261

R
2
=
1
26(2kHz)(500k)
=159pF
and
Low-pass Filter Example PSpice Simulation
Output Voltage Amplitude in dB
Output Voltage Amplitude in Volts (V) and Phase in Degrees (d)
Cascaded AmpliIiers
Connecting several ampliIiers in cascade (output oI one stage connected to
the input oI the next) can meet design speciIications not met by a single
ampliIier.
Each ampliIer stage is built using an op amp with parameters A. R
id
. R
o
,
called open loop parameters, that describe the op amp with no external
elements.
A
v
. R
in
. R
out
are closed loop parameters that can be used to describe each
closed-loop op amp stage with its Ieedback network, as well as the overall
composite (cascaded) ampliIier.
Two-port Model Ior a 3-stage Cascade
AmpliIier
Each ampliIier in the 3-stage cascaded ampliIier is replaced by its 2-port
model.


v
o
= A
vA
v
s
R
inB
R
outA
R
inB

'




+
'




A
vB
R
in
R
outB
R
in

'




+
'




A
v
v
A
vB
A
vA
A
v
A = =
s
v
o
v
Since R
out
0
R
in
R
inA
and R
out
R
out
0
A Problem: Voltage Follower Closed
Loop Gain Error due to A and CMRR
o
v
s
v
id
v =
2
o
v
s
v
ic
v

=


v
o
= A v
s
v
o
)

v
s
v
o
)
2(CMRR)

'



+
'



A
v
=
v
o
v
s
=
A1
1
2(CMRR)

'



+
'



1A1
1
2(CMRR)

'



+
'



The ideal gain Ior the voltage
Iollower is unity. The gain error
here is:


GE=1A
v
=
1
A
CMRR
1A1
1
2(CMRR)

'



+
'



Since, both A and CMRR are
normally ~~1,


GE
1
A

1
CMRR
Since A ~ 10
6
and CMRR ~ 10
4
at
low to moderate Irequency, the gain
error is quite small and is, in Iact,
usually negligible.
nverted R-2R Ladder DAC
A very common DAC circuit architecture with good precision.
Currents in the ladder and the reIerence source are independent oI digital
input. This contributes to good conversion precision.
Complementary currents are available at the output oI inverted ladder.
The 'bit switches need to have very low on-resistance to minimize
conversion errors.
Successive Approximation ADC
Binary search is used by the SAL to determine v
X
.
n-bit conversion needs n clock periods. Speed is
limited by the time taken by the DAC output to
settle within a Iraction oI an LSB oI J
FS
. and by the
comparator to respond to input signals diIIering by
small amounts.
Slowly varying input signals, not changing by
more than 0.5 LSB (J
FS
/2
n1
) during the
conversion time (T
T
nT

) are acceptable.
For a sinusoidal input signal with p-p amplitude
J
FS
,
To avoid this Irequency limitation, a high speed
sample-and-hold circuit is used ahead oI the
successive approximation ADC.
This is a very popular ADC with Iast conversion
times, used in 8- to 16- bit converters.

1
o

1
c
2
n2
(n1)6
SAADC: Block Diagram
SAADC: Method oI Operation