ECE/EEE/EIE Projects

N Karthik Hardware Engineer Intel India Pvt. Tech. Ltd., Bangalore (nkarthik12@gmail.com)

Overview
 

M.tech. Dissertation at IIT Bombay List of Projects that we handle



VLSI Projects
Digital Design  Analog Design


Embedded Projects

M.Tech. Dissertation

Fault Simulation Acceleration on an FPGA based Hardware Emulator



Fault Simulation  Simulating a circuit in the present of fault (stuck at 0/1)  Used for getting compact test set, fault dictionary, fault coverage

Inputs circuit

Outputs

G, Nf1, Nf2... Nfn | G, Nf1, Nf2... Nfn | i | i+1 |

ProtoProto-type Architecture on single FPGA

Recoded circuit With faults Injection elements

Controller & Test bench (HOST)

Restore Disable unit

Compare Block

Save-Restore block

Prototype Architecture on multiple FPGA

  

Circuit is partitioned into small parts so that it can be put into array of FPGA Each small circuit is wrapped up by controller called LEM (Local Evaluation Module) Global Scheduler keeps track of convergence of circuit and inject faults

LEM1

LEM2

LEM4

LEM3

Global Scheduler

Iteration Algorithm
begin Good Eval Iteration 1 fork New input Vector

Fault 1 Eval Iteration 1

Fault m Eval Iteration 1

join Good Eval Iteration 2 (converged) fork

Fault 1 Eval Iteration 2

Fault m Eval Iteration 2 (converged) join fork

Fault 1 Eval Iteration 2 (converged)

Fault m-1 Eval Iteration 2 (converged) ALL CONVERGED New input Vector

join Good Eval Iteration 1

VLSI Projects

Digital Design
       

Design of Basic Image Processing Filter using VHDL Design and Implementation of floating point ALU using VHDL Design of Memory Controller using VHDL Design of single cycle MIPS processor using VHDL Design of Error code generation, Error detection and correction logic using VHDL FPGA Implementation of Integer Wavelet Transform (IWT) algorithm Design of JPEG Decoder using VHDL Case Study of cache and Design of Cache eviction logic (LRU) using VHDL

Digital Design (contd..)



Software Tools required



Modelsim/ Ncsim/ VCS FPGA emulation board Basic Digital Design knowledge

Hardware Tools required (optional)



PrePre-requisite


Digital Design Steps (contd..)

   

Study on Algorithm and Specification (1 month) Bring up the Architecture (1 month) Coding in VHDL, simulating, testing (2 month) Porting code into FPGA [optional] ELSE we need to work on optimization for gate count and performance (1 month) Results, documentation and presentation (1 month)

Design of Basic Image Processing Filter using VHDL

         

Input/output bmp format (R8G8B8A8), test bench can extract pixels value and store in test bench memory with 1DW addressing Support 3x3, 5x5 kernel size User can provide coeff, and color map (RGBA) on which filter operation has to be performed Fixed point math Input data rate is 1 pixel/clk Output data rate is 1/3 pixel/clk for 3x3 map, 1/5 pixel/clk for 5x5 map Address generation logic should be in design To improve throughput cache can be used Develop C-code for testing CReference : Digital Image Processing by Gonzalez & Woods

Design and Implementation of floating point ALU using VHDL

     

Support basic operations such as ADD, MUL, DIV, SUB, MAC for 32-bit IEEE 754 floating-point input 32floatingSupport ADD, MUL, DIV, SUB, MAC for 32-bit 32integer point Indicate Overflow and Underflow conditions Should support +/-0, +/-infinity, NaN for floating +/- +/point numbers Develop C-code for testing CReference : Computer Orgnization and Architecture by William stallings

Design of Memory Controller using VHDL

        

4 requesting units (Device A,B,C,D), arbiter required (round robin/priority based user programming facility) Memory has 16-bit address range, 64KB 16Each device has its memory space allocated (16KB) Use dv-hold protocol dvStalls to device should be avoided, so need to use 4 deep fifo at input Output from memory is a global bus, and device is going to snoop on it based on TAG for read. Input data rate 1-request/clk/device, output data rate 111request/clk/device. Also provide facility for data protection for user provided address range Reference : Computer Orgnization and Architecture by William stallings

Design of single cycle processor using VHDL



A single cycle processor executes one instruction per clock cycle including fetching the instruction, decoding the instruction, fetching operands from the register le, perform computation in ALU, and finally writing back the result Support MIPS (Microprocessor without Interlocked Pipeline Stages) instruction set (9 I-type, 9 R-type instruction) Input is a asm file, output is results

Analog Design
         

A Novel high speed dynamic comparator with low power dissipation and low offset Design of Low-Power CMOS Ramp Generator for DC-DC LowDCConverters Comparative Study Of CMOS Voltage Controlled Oscillator Design of LC-Voltage Controlled Oscillator LCDesign of Multi-Modulus Frequency Divider for DVB-H MultiDVBReceiver Phase Interpolator CML Freq divider 50MHz 8 bit Folding and Interpolating ADC (GPIO/USB/PCI-E)Transmitter Design (GPIO/USB/PCIDesign and Simulation of different Types CMOS Phase Frequency detectors for high Speed and low JITTER PLL

Analog Design (contd..)



Software Tool Required



Cadence Analog Artist Basic Analog Design Knowledge

PrePre-requisite


Embedded Projects

Thank You