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3.1 - Overview of displaying images in a Graphics System 3.1 - Block diagram of Video Subsystem & port connector 3.2 - Video Display Modes in a Graphics System 3.2 - Text Mode Video Buffer data format & character fonts. 3.2 - The attribute byte & the palette registers 3.2 - Color generation using the Video DAC 3.3 - The Graphics Mode Video Buffer data format.
Video Subsystems
This
section focuses on the VGA standard which was introduced by IBM in 1987 and is commonly used today.
This information is generic in nature and may not apply in some video modes or adapter configurations.
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Register functions used primarily by programmers and color/ mono differences are beyond the scope of this course.
There
Video Subsystems
The PC Video Graphics Controller is responsible for producing the image that is displayed on the screen.
This
hardware can be located on the System Board or on an add in card called a Graphics Adapter or Display Adapter that plugs into an expansion slot (PCI, ISA, etc). PC Video Subsystem contains a block of dedicated memory called the Video Buffer, Video Memory, Display Memory or Video RAM.
The
This Display Memory holds the text or graphics information to be displayed on the screen.
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A primary function of the VGA Controller is to serialize the data in its display memory and to mix this stream of data with synchronizing signals that control the video display.
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An O/S (DOS, Windows, etc.) and/or Application program (word processor, game, etc.) updates information on the screen using the Video BIOS or a Video Device Driver.
An
installable Device Driver is a program that works with the O/S to translate commands that control a piece of hardware, typically for extended functions not supported by standard hardware.
Operating System Applications
SOFTWARE
Microprocessor
Video Controller
Graphics Subsystem
HARDWARE
DISPLAY
PC RAM / ROM
Video Memory
DAC
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special section of display memory called the Video Buffer (separate from main system memory) stores data that will appear on the screen.
This memory is accessed via the Video Subsystem by the CPU as well as the Video Controller, permitting a program to change the display screen by updating the contents of the display memory. The video is commonly displayed on a Monitor which converts the synchronizing and video signals from the graphics sub-system into the proper form for display use.
Digital
signals are used internally by the Controller, and VGA and later uses analog signals to drive the Display.
The Digital to Analog Converter (DAC) converts the color information supplied by the VGA chip to analog voltages for the red, green, and blue gun outputs to the monitor. 7
Microprocessor
41h
41 07
Attribute Decoder
CRT Controller
Video RAM
Video Controller
NOTE: The Video Signal Gen & Alphanumeric Char. Gen functions are performed by more than one of the programmable components in the VGA block diagram discussed later in this chapter.
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Decodes memory addresses to Video Memory or I/O addresses to the VGA registers.
The
Generates the horizontal and vertical timing signals that control the path and duration of the electron beam sweeping the inner surface of the CRT.
Display
memory
The Video Buffer contains the information to be displayed on the screen & is effectively a large shift register sending a serial data stream to the monitor.
Alphanumeric
Translates the ASCII value of a character stored in the video buffer into a matrix of dots to display on the screen.
Attribute Decoder:
Controls the color and brightness of the signals sent to the monitor.
Video
Signal Generator:
Horiz sync (to 90 KHz) Vert sync (50 - 120Hz) Three possible kinds of video signals are: Digital (CGA, EGA) - Digital RGB monitors accept TTL level signals for red, green, or blue on separate lines. Analog (VGA) - Analog RGB monitors accept 0-0.7V analog signals for red, green and blue on separate lines. Composite (also used for TV) - The red, green, and blue are combined by the video subsystem and separated by the monitor.
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Focusing system
Heating filament
Cathode
rear part of the CRT contains a cathode that emits an electron beam when heated.
A color monitor has three adjacent electron beams (Red, Green, & Blue) which can be regarded as a single beam.
The
In a color monitor, there are three adjacent phosphor dots (a triad) called a PEL or PIXEL (Picture Element) laid out in horizontal scan lines.
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Dot Pitch indicates the distance between triads (e.g.-0.28 mm) and is a measure of the resolution of the monitor. Typical ranges is 0.15 mm to 0.40 mm
When the intensity modulated electron beam strikes the phosphor coated inner surface of the CRT, it changes the brightness of the CRTs glow. 12
CRTs electron beam sweeps across the screen in a fixed path from left to right (Horizontal) and top to bottom (Vertical).
These lines are continually scanned many times a second producing a uniform pattern of closely spaced horizontal lines (called a raster) which covers the entire screen.
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The CRT image must be redrawn continuously because it will remain visible for only a few milliseconds depending on the persistence of the phosphor.
With
additive mixing of the 3 primary colors, all known colors can be generated
Mixing equal parts of red, green & blue produces shades of white light.
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an interlaced graphics system, it takes 2 fields (1 odd, 1 even) to display one complete screen (called a frame)
Interlaced mode is used when the monitor cannot keep up with the data rates required by the video system--used for the first 1024x768 displays.
non-interlaced display has an entire frame displayed each screen refresh--every line is updated every frame.
Non-interlaced displays produce a more pleasing screen image (less flicker) than interlaced displays.
Note:
Angle of scan line is exaggerated
Horizontal Deflection
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Horizontal Retrace
Note:
Angle of scan line is exaggerated
Time
Horizontal Deflection
The first field consists of only the odd numbered line. The next field consists of only the even numbered lines.
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The TV rate is 2:1 interlace - 60 fields/sec; 30 frames/sec A 30 frame-per-second rate would noticeably flicker, while the effective 60 frame-per-second rate does not. The human eye recognizes the the alternate scanlines as one image because it cant resolve the flickering of images refreshed more than 50 time per second.
The
advantage of interlacing is that the frame rate (and the video B/W) is half of what would be required to display this same resolution in non-interlaced mode.
Interlacing results in the ability to display a resolution that would be impossible for hardware in non-interlaced mode. Interlacing enables a monitor to provide more resolution inexpensively.
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Video Display Modes: Video subsystems operate in multiple display modes which control certain aspects of the video operation.
Text
OR Graphics:
Text modes display alphanumeric characters only. Graphics modes are bit-mapped (All Points Addressable)
Screen
Number Note:
The initial video mode is an 80-column Text mode (03h) set by the ROM BIOS during POST.
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The information written to the video buffer by the microprocessor is represented on the screen as a pattern of illuminated dots called pixels.
The
microprocessor writes information to the video hardwares display buffer in either alphanumeric or graphics format.
Each location on the video screen maps to a location in the display RAM.
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The
first location of the display buffer maps to the top, leftmost point on the screen. memory addresses increase, the screen location move from left to right & top to bottom.
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As
The
microprocessor writes each symbol (letter, number, etc) as a series of 2 bytes (character & attribute) into the Video Memory.
The first byte represents the characters ASCII value The second byte represents the characters attribute (i.e. color, foreground/background, blinking, intensity)
Video
hardware translates the character & attribute bytes to the necessary series of dots.
Characters
are painted on the screen in a matrix of dots called a character box or character cell.
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42h 07h
43h 07h
SCREEN
Mapping from the display memory to the screen. Segment B800 - Text Mode
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Also
The
microprocessor writes the individual color value of each pixel to be painted on the screen.
All pixels can be controlled independently to draw graphics objects (as opposed to Text Mode, in which only a pre-defined set of characters can be displayed.
The
microprocessor must address the display buffer as a memory map of a series of bits (bytes for Text mode).
The
Video hardware generates the color & control signals necessary to illuminate the dot at the correct location on the screen.
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The following block diagram will introduce the typical functions of a VGA Video Controller. The following is a generic description to show the relationship between components of the VGA Video Controller. Note that many of the components of the video controller interact and this can be represented with different interconnect configurations.
You
may see the following blocks grouped and/or connected in different ways, depending on the vendor and the level of detail shown.
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A video display adapter contains the following basic elements (usually implemented in an ASIC):
Host
Interface
Clock CRT
Controller (CRTC): [Ports 3D4, 3D5] Memory (Video Buffer) [A000:0 - B000:FFFF]
Memory Display
[3C7 (PEL Addr Rd); 3C8 (PEL Addr Wr); 3C9 (Pixel Data)] BIOS (Not implemented in ASIC)
Mem Clock
Vertical Timing
CRT
Addr Ctrl
Video Memory
Dot Stream To Monitor R G
Optional
Clock
S Y N T H
Graphics Controller
FIFO
Feature Connector
System Interface:
Decodes memory addresses to the Video Memory OR I/O addresses to the Video Controller registers.
The
Frequency Synthesizer:
Generates frequencies from a fixed source (e.g. 14.3 MHz). Programmed to generate the VCLK & MCLK.
>
>
Video (Pixel, Dot) Clock: VCLK range (25-135MHz) This determines the Video Bandwidth MCLK (Memory Clock): MCLK range (35-80 MHz) Used by the Memory Sequencer
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The Cathode Ray Tube Controller maintains screen refresh functions for the various display modes.
Generates
These control the path and duration of the electron beam sweeping the inner surface of the CRT.
Generates
The CRTC selects the portion of the video buffer to be displayed on the screen.
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The CRTC synchronizes the Video Buffer address counter with the Horizontal and Vertical timing signals.
Controls
the size & location of the text mode cursor & generates the Cursor & underline timing signals
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Memory Controller:
Generates the signals & addresses for accessing display memory and provides mapping of the Video Memory.
The
Memory Arbitrator:
Ensures that the necessary screen refresh & DRAM refresh cycles are executed.
The Video Buffer may be accessed by 3 resources:
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>
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The Video Output Circuitry: Stream of data to redraw display (~ 80% of mem accesses) The Host computer: Accesses the memory to update the screen. The DRAM Refresh circuitry
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The Video Buffer is a block of RAM that exists on the adapter but is mapped into the microprocessors address space.
The
The video circuitry refreshes the screen by continually and repeatedly reading the data in the video RAM.
Address The
actual size of the Video Buffer varies with video subsystem: 64KB to 4 MB (or more).
Most PC subsystems have enough DRAM to hold more than one screen of displayable data, so only part of the Video Buffer is visible on the screen.
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is the most popular - (Fast Page or EDO) (Video RAM) - Dual-ported RAM
The adapter can fetch the contents of memory for display at the same time that new data is being put into memory.
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The CPU use the parallel port for random reads & writes The adapter updates the display by reading the serial port.
WRAM
Similar to VRAM, but has faster performance at less cost. Can synchronize itself with the CPU bus clock and can open 2 memory pages at once which simulates dual-port 30 RAM.
SGRAM
The Graphics Controller manipulates data flow between the CPU and the Video Buffer.
Provides
Controls
the data flow between the Display Memory and the Attribute Controller--video to monitor.
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The optional video FIFO supplies data to the Attribute Ctlr as required, allowing memory accesses at maximum memory speed rather than the screen refresh rate.
video memory data from the graphics controller & formats the data for display on the CRT. palette controls the color and brightness of the signals sent to the monitor.
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The
three (RGB) DACs (or RAMDACs) which interface directly to the monitor connector via RFI filters.
Converts
the color palette information supplied by the VGA chip to the correct analog voltages to be placed on the red, green, and blue gun outputs to the monitor.
Video DAC uses the 8-bit input to select one of its 256 color registers (256 different colors at one time). of DACs 256 color registers contains an 18-bit RGB specification (6-bits for each color)
The
Each
Note: SVGA DACs can use 8 bits per color (24 bits / pixel)
The optional Feature Connector provides support for synchronizing graphics output with external devices.
Permits
third party add-on accessories to share signals and control of the VGA circuitry.
Permits direct transfer of video information between the video card and other video devices (3D accelerators, video capture cards, etc), without having to use the system bus. Also can be used to send signals to a 2nd higher resolution video card that has its own high-performance RAMDAC.
Pixel
data, Horizontal & Vertical Sync, and Dot Clock signals are available on the feature connector.
Video Feature Connector (VFC), VESA Advanced Feature Connector (VAFC), and VESA Media Channel (VMC) .
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Video BIOS contains a set of well-documented, easy to use routines that provide a low-level programming interface for accessing the hardware and provides compatibility across different hardware platforms.
Applications should make requests through BIOS calls rather than communicating directly with hardware. Software Interrupt 10 hex is used for Video BIOS routines (e.g. - Set Mode, Write character, Move Cursor, etc.)
The
Video BIOS on adapter cards is found during the POST expansion ROM detection (at address C000:0)
The C000 Segment Video BIOS routines usually augment or replace any System BIOS (F000 Seg) video routines.
> >
The INT 10h IVT is re-routed to the Video adapter (C000:xxxx) INT 42h replaces the default INT 10h IVT (F000:xxxx).
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1 2 3 4 5
10
Video Signal Levels: Black = 0v, Full Intensity = +0.7V Monitor ID bits are used to automatically sense the type of monitor installed on power up.
The VGA uses a 15 pin D-Shell connector to interface with the monitor.
The
analog & digital signals are meant to drive an analog color or analog monochrome monitor.
The DAC outputs analog Red, Green, & Blue Video signals to the monitor guns (RS-170).
Black = 0v
Full Intensity = +0.7V Monochrome monitors use the Green Video for all input.
The
RGB lines are terminated in a 75 ohm load at the Graphics Controller and a 75 ohm load at the monitor.
Sync signals are TTL level and polarity were used by the older monitors to determine the video mode for screen sizing (Monitor uses to adjust vertical gain).
e.g.
e.g.
Some
newer monitors analyze the sync signals to determine the video mode or use the Plug & Play VESA DDC standard.
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Monitor ID bits [MID3:0] are used to sense the type of monitor installed by the BIOS on power up.
Pulled
Not
DDC2B-Compliant Monitors
Monitor
pins MID1 & MID 3 become DDC Data & DDC Clock lines for this serial communications protocol. DDC (Display Data Channel) spec defines a serial communications channel between a computer display and a host system.
The
Allows the monitor, video card, & the O/S to communicate. Windows 95's Plug and Play architecture supports DDC.
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VESA has defined a standard method for the computer to tell the monitor when to go to power saving mode.
This
shuts off the deflection & high voltage in the monitor, but the CRT filament remains lit.
The power saving mode is controlled by changing the sync signals according to the list below:
H-sync ON; V-sync ON: Normal (Power Level 100%)
PC Video Graphics Controller is responsible for producing the image that is displayed on the screen. O/S and/or Application updates screen information the using the Video BIOS and/or a Video Device Driver.
An
The
PC Video Subsystem contains a block of dedicated Display Memory that holds the text or graphics information to be displayed on the screen.
VGA Controller serializes the data in its display memory and mixes this stream of data with synchronizing signals that control the video display.
40
The
rear part of the CRT contains a cathode that emits an electron beam when heated and the front surface of a computer monitor is actually the end of a large CRT. CRTs electron beam sweeps across the screen in a fixed path from left to right and top to bottom.
The
The CRT image must be redrawn continuously because it will remain visible for only a few milliseconds depending on the persistence of the phosphor.
In
an interlaced graphics system, it takes 2 fields (1 odd, 1 even) to display one complete screen (called a frame). non-interlaced display has an entire frame displayed each screen refresh--every line is updated every frame.
41
Basic elements usually implemented in an ASIC. Point & Shoot is used to access registers.
Mem Clock
Vertical Timing
CRT
Addr
Ctrl
Video Memory
Dot Stream To Monitor
R G
Optional
Data
Clock
S Y N T H
Dot Clock
Graphics Controller
FIFO
Feature Connector
The
DAC outputs analog Red, Green, & Blue Video signals to the monitor guns. 42 End of Chapter 3-1