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Input/Output
Organization
Computer Organization
Overview
Computer has ability to exchange data with
other devices.
Human-computer communication
Computer-computer communication
Computer-device communication
…
Accessing I/O Devices
Single Bus
Processor Memory
Bus
I/O device 1 I/O device n
Figure 4.1. A singlebus structure.
Memory-Mapped I/O
When I/O devices and the memory share the same
address space, the arrangement is called memory-
mapped I/O.
Any machine instruction that can access memory
can be used to transfer data to or from an I/O
device.
Move DATAIN, R0
Move R0, DATAOUT
Some processors have special In and Out
instructions to perform I/O transfer.
Interface
Address lines
Bus Data lines
Control lines
Input device
Figure 4.2. I/O interface for an input device.
Program-Controlled I/O
I/O devices operate at speeds that are vastly
different from that of the processor.
Keyboard, for example, is very slow.
It needs to make sure that only after a
character is available in the input buffer of the
keyboard interface; also, this character must
be read only once.
The basic idea is to set a status flag, SIN, as
part of the status register.
Keyboard Control Example
DATAIN
DATAOUT
7 6 5 4 3 2 1 0
e 4.4 A program that reads one line from the keyboard stores it in memory buffer, and echoes it back to the dis
Three Major Mechanisms
Program-controlled I/O – processor polls the
device.
Interrupt
1
2
Interrupt
occurs i
here
i +1
Figure 4.5. Transfer of control through the use of interrupts.
Several Points
Interrupt-service routine – PRINT
Store the current PC
Return-from-interrupt
Interrupt-acknowledge signal
Interrupt latency
Real-time processing
R
INTR
INTR
Figure 4.6. An equivalent circuit for an opendrain bus used
to implement a common interruptrequest line.
Enabling and Disabling
Interrupts
Since the interrupt request can come at any
time, it may alter the sequence of events from
that envisaged by the programmer.
Interrupts must be controlled.
INTR 1 I NTR p
Processor
INTA1 INTAp
Priority arbitration
circuit
Figure 4.7. Implementation of interrupt priority using individual
interruptrequest and acknowledge lines.
Simultaneous Requests
I NTR
Processor
Device 1 Device 2 Device n
INTA
(a) Daisy chain
I NTR 1
Device Device
INTA1
Processor
INTR p
Device Device
INTAp
Priority arbitration
circuit
(b) Arrangement of priority groups
Figure 4.8. Interrupt priority schemes.
Controlling Device Requests
Some I/O devices may not be allowed to
issue interrupt requests to the processor.
At device end, an interrupt-enable bit in a
control register determines whether the
device is allowed to generate an interrupt
request.
At processor end, either an interrupt enable
bit in the PS register or a priority structure
determines whether a given interrupt request
will be accepted.
Exceptions
Recoveryfrom errors
Debugging
Trace
Breakpoint
Privilege exception
Use of Interrupts in Operating
Systems
The OS and the application program pass
control back and forth using software
interrupts.
Supervisor mode / user mode
Multitasking (time-slicing)
Program state
OSINIT Setinterruptvectors:
Time-sliceclock ← SCHEDULER
Softwareinterrupt ← OSSERVICES
Keyboard interrupts ← IOData
..
.
OSSERVICES Examinestack todetermine requestedoperation.
Callappropriate routine.
SCHEDULER Saveprogramstate.
Selectarunnableprocess.
Restoresaved context of newprocess.
Pushnew valuesfor PS and PCon stack.
Returnfrom interrupt.
(a) OS initialization, services, and scheduler
(b) I/O routines
KBDINIT Enableinterrupts.
Returnfromsubroutine.
KBDDATA Checkdevicestatus.
If ready, thentransfercharacter.
If character= CR, then{set END = 1;Disablein
terrupts }
elsesetEND= 0.
Returnfromsubroutine.
(c) Keyboard driver
T S X N Z V C
Trace
Condition
Interrupt Codes
Supervisor
Priority
Figure 4.15. A 68000 interrupt-service routine to read an input line from a keyboard based on Figure 4.9.
DMA
Think about the overhead in both polling and
interrupting mechanisms when a large block of data
need to be transferred between the processor and
the I/O device.
A special control unit may be provided to allow
transfer of a block of data directly between an
external device and the main memory, without
continuous intervention by the processor – direct
memory access (DMA).
The DMA controller provides the memory address
and all the bus signals needed for data transfer,
increment the memory address for successive
words, and keep track of the number of transfers.
DMA Procedure
Processor sends the starting address, the number of
data, and the direction of transfer to DMA controller.
Processor suspends the application program
requesting DMA, starts DMA transfer, and starts
another program.
After the DMA transfer is done, DMA controller
sends an interrupt signal to the processor.
The processor puts the suspended program in the
Runnable state.
DMA Register
31 30 1 0
Status and control
IRQ Done
IE R/ W
Starting address
Word count
System bus
Disk/DMA DMA
controller controller Printer Keyboard
Figure 4.19. Use of DMA controllers in a computer system.
Memory Access
Memory access by the processor and the
DMA controller are interwoven.
DMA device has higher priority.
Among all DMA requests, top priority is given
to high-speed peripherals.
Cycle stealing
Block (burst) mode
Data buffer
Conflicts
Bus Arbitration
The device that is allowed to initiate data
transfers on the bus at any given time is
called the bus master.
Bus arbitration is the process by which the
next device to become the bus master is
selected and bus mastership is transferred to
it.
Need to establish a priority system.
Two approaches: centralized and distributed
Centralized Arbitration
B BS Y
BR
Processor
DMA DMA
controller controller
BG1 1 BG2 2
BR
BG1
BG2
B BS Y
Bus
master
Processor DMA controller 2 Processor
ARB 3
ARB 2
ARB 1
ARB 0
StartArbitration
O.C.
0 1 0 1 0 1 1 1
Interface circuit
for device A
Figure 4.22. A distributed arbitration scheme.
Buses
Overview
The primary function of a bus is to provide a
communications path for the transfer of data.
A bus protocol is the set of rules that govern the
behavior of various devices connected to the bus as
to when to place information on the bus, assert
control signals, etc.
Three types of bus lines: data, address, control
The bus control signals also carry timing
information.
Bus master (initiator) / slave (target)
Synchronous Bus Timing
Time
Bus clock
Address and
command
Data
t0 t1 t2
Bus cycle
Figure 4.23. Timing of an input transfer on a synchronous bus.
Synchronous Bus Detailed
Timing Time
Bus clock
Seen by master t AM
Address and
command
Data
t DM
Seen by sla ve
tAS
Address and
command
Data
tDS
t0 t1 t2
Figure 4.24. A detailed timing diagram for the input transfer of Figure 4.23.
Multiple-Cycle Transfers
Time
1 2 3 4
Clock
Address
Command
Data
Slaveready
Address
and command
Masterready
Slaveready
Data
t0 t1 t2 t3 t4 t5
Bus cycle
Figure 4.26. Handshake control of data transfer during an input operation.
Asynchronous Bus – Handshaking
Protocol for Output Operation
Time
Address
and command
Data
Masterready
Slaveready
t0 t1 t2 t3 t4 t5
Bus cycle
Figure 4.27. Handshake control of data transfer during an output operation.
Discussion
Trade-offs
Simplicity of the device interface
Ability to accommodate device interfaces that introduce
different amounts of delay
Total time required for a bus transfer
Ability to detect errors resulting from addressing a
nonexistent device or from an interface malfunction
Asynchronous bus is simpler to design.
Synchronous bus is faster.
Interface Circuits
Function of I/O Interface
Provide a storage buffer for at least one word of
data;
Contain status flags that can be accessed by the
processor to determine whether the buffer is full or
empty;
Contain address-decoding circuitry to determine
when it is being addressed by the processor;
Generate the appropriate timing signals required by
the bus control scheme;
Perform any format conversion that may be
necessary to transfer data between the bus and the
I/O device.
Parallel Port
A parallel port transfers data in the form of a
number of bits, typically 8 or 16,
simultaneously to or from the device.
For faster communications
Parallel Port – Input Interface (Keyboard
to Processor Connection)
Data
Address
DATAIN Data
Encoder
R /W and Keyboard
Processor SIN
debouncing switches
Masterready circuit
Valid
Input
Slaveready
interface
Figure 4.28. Keyboard to processor connection.
DATAIN
D7 Q7 D7
Keyboard
data
D0 Q0 D0
SIN
Status Valid
flag
Slave
ready 1
Read
status
Read
data
R/ W
Master
ready
A31
Address
decoder
A1
A0
Data
Processor
CPU R /W SOUT Printer
Valid
Masteready
Output Idle
Slaveready interface
Figure 4.31. Printer to processor connection.
Bus
D7 PA7
DATAIN
D1
D0 PA0
SIN
Input
status CA
PB7
DATAOUT
PB0
SOUT
Handshake CB1
control CB2
Slave
Ready 1
Master
Ready
R/ W
A31
Address Myaddress
decoder
A2
RS1
A1
RS0
A0
Figure 4.33. Combined input/output interface circuit.
D7 P7
DATAIN
D0 P0
DATAOUT
Data
Direction
Register
Myaddress
RS2
RS1 Status C1
Register
RS0 and
select control
R /W C2
Ready
Accept
INTR
1 2 3 4
Clock
Address
Command
Data
Slaveready
D7 D7 Q7
Printer
data
D0 D1 Q1
D0 D0 Q0
SOUT
Handshake Idle
control Valid
Read Load
status data
R/W
Slav e
ready
Go
A31
Address Myaddress Timing
decoder Logic
A1
A0
Clock
Myaddress
Idle Respond
Go=1
Figure 4.35. A parallel point interface for the bus of Figure 4.25,
with a statediagram for the timing logic.
Serial Port
A serial port is used to connect the processor
to I/O devices that require transmission of
data one bit at a time.
The key feature of an interface circuit for a
serial port is that it is capable of
communicating in bit-serial fashion on the
device side and in a bit-parallel fashion on
the bus side.
Capable of longer distance communication
than parallel transmission.
Serial
Input shift register input
DATAIN
D7
D0
DATAOUT
Myaddress
RS1
RS0 Chip and
register Serial
R /W Output shift register output
select
Ready
Accept
Receiving clock
Status
I NTR and
control
Transmission clock
Expansion bus
Processor bus
Bridge
PCI bus
SCSI bus
IDE
disk
Video
Disk CDROM
controller controller
CD
Disk 1 Disk 2 ROM K eyboard Game
Figure 4.38. An example of a computer system using different interface standards.