Texas Instruments

C5000
TMS320 One-Day DSP Workshop

Administrative Topics

Instructor Introduction Materials (whats in front of you and what you get to take home) Bathrooms, Exits Mute cellular phones/pagers Please let the instructor(s) know if you have any special needs
Lets GO...

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What Will We Accomplish Today?

Overview C5000 architecture and peripherals

Use Code Composer Studio and Visual Linker to edit, build and debug applications
Understand how to achieve highest performance using advanced features and DSPLIB functions Use BIOS and RTDX to build,analyze and debug a DSP system Run labs using common applications on real hardware (the DSK)
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The Agenda
1. C5000 Architecture, CCS, Visual Linker Lab1 Use CCS to build and debug code
2. Achieving High Performance With Ease Lab2 Implement and measure high performance 3. Real-Time Scheduling/Debug Using BIOS and RTDX Lab3 Use BIOS to build and debug a system Use RTDX to send data to a running system

Oh, and dont forget about breaks and lunch

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Want To Learn More About DSP?

A Simple Approach to Digital Signal Processing by Craig Marven and Gillian Ewers; ISBN 0-4711-5243-9

DSP Primer (Primer Series) by C. Britton Rorabaugh; ISBN 0-0705-4004-7

"A DSP Primer : With Applications to Digital Audio and Computer Music by Ken Steiglitz; ISBN 0-8053-1684-1

"DSP First : A Multimedia Approach (Matlab Curriculum Series) James H. McClellan; ISBN 0-1324-3171-8

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Different needs, Many families

C6000
(C62x,C67x,C64x)

C5000
(C54x, C55x) C5x

C3x C4x C8x

C2000
(C20x,C24x,C28x)
C1x C2x

Highest Performance
Multi Channel, Multi Function Comm Infrastructure xDSL Imaging, Video

Highest Efficiency
Best MIPS per: Watt / Dollar/ Size Wireless Clients Modems / Telephony VoIP

Lowest Cost
Control Systems Storage Motor Control T TO
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The C54x Family

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What Can the C54x Family Deliver?

Most power efficient DSP family in the industry Ultra small packaging (BGA, TQFP) Small code size

Low cost (starting at $5)

Single core performance up to 160 MIPS Multi-core performance up to 532 MIPS
Migrate client software to server systems

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Up to 8Mwords of program space

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C5000 1-Day Workshop

Module 1
C5000 Architecture, CCS, Visual Linker

What Problems Are We Trying To Solve?

Amplitude

Data Read Buses

MAC x4 x3 x2 x1 x0
Time

ALU A

y 0 = a nx n
n=0 MAC *AR2+, *AR3+, A T TO
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z = x2 + x4 + x3 + x1

Single-cycle MAC Single-cycle ADD

ADD @x2, B ...

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C5402 Architecture (10km view)

Data Read A/D Bus (C) Program A/D Bus (P) Data Read A/D Bus (D) PC XPC DP Decode @x2
Addr Gen

MAC AR0-7 A B Data Write A/D Bus (E)

ALU

MAC *AR2+, *AR3+, A T TO

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ADD @x2, B ...

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C5402 Block Diagram

17x17 MAC Unit
Saturation and Rounding Hardware Two 40-bit ACCs 40-bit ALU

40-bit Barrel Shifter

Temporary Register Exponent Encoder Program and Data Address Generation Units Compare, Select and Store Unit 4 Internal Bus Pairs

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External Interface
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Pipeline Drives Single-Cycle Performance

Pipeline Phases P - generate program address F - get opcode from prog mem D - decode instruction A - generate data read address R - get operands from data mem X - execute instruction P F D A P F D P F P R A D F P X R A D F P X R A D F

X R X A R X D A R X

Full Pipeline

Pipeline One

phases maximize hardware usage

instruction is retired EVERY cycle

Dedicated

loop control instructions (RPT and RPTB) available to reduce pipeline flushing
How does the architecture support pipelining?
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C5402 Internal Memory and Buses

4Kx16 0-wait ROM 2x8Kx16 0-wait DARAM

5402DSK Memory Resources

64Kx16 1-wait SRAM 256Kx16 7-wait FLASH

P Bus D Bus C Bus E Bus

Extl Mem I/F

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ROM - 1 access per block per cycle DARAM - 2 accesses per block per cycle External - 1 access every other cycle Wait States are shown for 100MHz clock
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T TO Lets take a closer look at the program memory resources...

C5402 DSK Program Memory

Program Memory
00 0000 00 4000 00 FFFF 03 0000 03 4000 03 FFFF T TO
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C5402 can address up to 1Mx16 of program memory OVLYbit=0 on reset (all program is external) DSK uses the following:

16K DARAM Upper 48K Page 0 Flash

. . .
16K DARAM Upper 48K Page 3 Flash

OVLYbit=1: 16K DARAM mapped to ALL Program Mem Pages (access as data/prog) Allows access to 0-wait memory for code Only 256K of 1M total address reach of C5402 is physically implemented

Lets take a closer look at the data memory resources...

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C5402 DSK Data Memory

0000 0060 0080 MMRs SPRAM ~8Kx16 DARAM Block 1 8Kx16 DARAM Block 2

C5402 can access 64Kx16 data All internal accesses are 0-wait User should partition algorithm resources to avoid memory access conflicts Can access most CPU registers via memory-mapped locations (MMR)

2000

4000

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External 48Kx16 1-wait SRAM

C5402 can also access 64Kx16 I/O

What internal peripherals are on the C5402 ?

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Peripheral Overview
C54x CPU

C5402
2 Multi-Channel BSPs: Each offers up to 128-channel rcv/xmt 6-channels: facilitates transfers without CPU intervention Host Port Interface: 8-bit interface to host processor Boot Loader: Multiple ways to load program to volatile memory Two 20-bit timers: Can generate timed-based interrupts General Purpose I/O: 4 dedicated and 16 multipurpose pins Phase Locked Loop: software programmable Idle Modes: Power saving modes and features

McBSP DMA EHPI

Boot
Timers GPIO PLL

Pwr Down

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What does the DSK look like?

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DSK (DSP Starter Kit) Block Diagram

Terminal
UART/ RS-232

64Kx16 1ws SRAM

256Kx16 7ws Flash

Daughter-board Expansion Bus

EMIF
TLC320 AD50 AIC

PC

5402

Parallel Port

CCS

D A A

TLC320 AD50 AIC

CPLD

JTAG

XDS-510 Emulator

DSK includes: DSK board, power supply, DSK-specific CCS, parallel cable, docs T TO
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Now lets take a look at Code Composer Studio...

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Powerful, Easy-To-Use IDE: CCS

Code

Composer Studio

Integrates: edit, code gen, debug Single-click access using buttons

Powerful graphing/profiling tools

Automates tasks using GEL scripts Built-in access to BIOS functions Supports TI or 3rd party plug-ins What is a Project ?

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A Project Is...

Code Composers .pjt file

Includes all of the necessary source files to BUILD code
Include (headers, other) Libraries (run-time support) Linker Command Assembly C

Simply ADD the necessary files and BUILD to create an executable output file

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T TO How does CCS know about the users memory resources ?

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Visual Linker

Integrated CCS Plug-In Drag and Drop Operation Graphical Interface Explorer Views Convert older .cmd files

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What is the linking process ?

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Translating Relative to Absolute Addresses

Input Files
FFT.asm vars1 vars2 code1 vars1 vars2
2000h

Memory Map Output File

VARS Write .OUT

Main.C vars1 code2 code3 Relative

code1 code2 code3

3000h

CODE

Absolute

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Visual Linker uses addresses provided by the memory map to place relocatable sections from input files into output sections in an executable output file.
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Lab1 - Getting to Know (and Love) CCS

Application: Audio Pass Through What you will learn: Basic CCS Debug, Visual Linker Hardware Diagram...

C5402
AIC
ADC midi

McBSP1
REVT1

In_Buf
Copy
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DMAC2

DRR1
DXR1
DAC
XEVT1

1 2 3

Out_Buf DMAC3
1 2

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Lab1 - Getting to Know (and Love) CCS

Software Flow:
LAB1.C DMAC2ISR.ASM
Determine frm cnt (1,2 or 3) frame_count += 1 frame1: set I/O addresses B out frame2: set I/O addresses B out frame3: set I/O addresses out: Xfr In_Buf to Out_Buf Turn on DMAC3 for output return

Init DSK Board Blink LEDs Init McBSP/AIC Init DMAC2 Set reload registers for DMAC2 Forever Loop

DMAC2 Int T TO
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