Combinational Circuits:

Design Methods/Arithmetic
Circuits
 Introduction
 Analysis Procedure
 Design Methods
 Gate-level (SSI) Design
 Half Adder
 Full Adder
 BCD-to-Excess-3 Code Converter

 Block-Level Design
 4-bit Parallel Adder
 BCD-to-Excess-3 Code Converter
 16-bit Parallel Adder
 4-bit Parallel Adder cum Subtractor
 Combinational Circuits:
Design Methods/Arithmetic
Circuits
 Arithmetic Circuits
 Adders
 Parallel Adders
 Cascading Adders
 Parallel Adder-Subtractor
 Comparator
 Propagation Delays
 Calculations of Circuit Delays
 Faster Circuits
 Look-Ahead Carry Adder
Introduction
 Two classes of logic circuits:
 combinational
 sequential

 Combinational Circuit:

inputs Combinational outputs

:: Logic
::

Each output depends entirely on the immediate

(present) inputs.
Introduction
 Sequential Circuit: (to be covered later)

inputs Combinational outputs

:: Logic
::

Memory
Output depends on both present and past inputs.
Memory (via feedback loop) contains past
information.
Analysis Procedure
 Given a combinational circuit, can you analyze its
function?
A A+B
B F1 = (A+B).(A'+B')

F2 = (A'+B')' = A.B
A'+B'
A B (A+B) (A'+B') F1 F2
Steps: 0 0 0 1 0 0
1. Label the inputs and outputs. 0 1 1 1 1 0
1 0 1 1 1 0
2. Obtain the functions of 1 1 1 0 0 1
intermediate points and the outputs.
3. Draw the truth table.
4. Deduce the functionality of the circuit ➜ half adder.
Design Methods
 Different combinational circuit design methods:
 Gate-level method (with logic gates)
 Block-level design method

 Design methods make use of logic gates and

useful functional blocks.
 These are available as Integrated Circuit (IC) chips.
Design Methods
 Type of IC chips (based on packing density) :
 Small-scale integration (SSI): up to 12 gates
 Medium-scale integration (MSI): 12-99 gates
 Large-scale integration (LSI): 100-9999 gates
 Very large-scale integration (VLSI): 10,000-99,999 gates
 Ultra large-scale integration (ULSI): > 100,000 gates
 Main objectives of circuit design:
 (i) reduce cost
 reduce number of gates (for SSI circuits)
 reduce IC packages (for complex circuits)

 (ii) increase speed

 (iii) design simplicity (reuse blocks where possible)
Gate-level (SSI) Design: Half Adder
 Design procedure:
1) State Problem
Example: Build a Half Adder to add two bits
2) Determine and label the inputs & outputs of circuit.
Example: Two inputs and two outputs labelled, as
follows:
X Y C S
X S 0 0 0 0
Half
0 1 0 1
Y Adder C 1 0 0 1
1 1 1 0
(X + Y)

3) Draw truth table.

Gate-level (SSI) Design: Half Adder
4) Obtain simplified Boolean X Y C S
0 0 0 0
function. 0 1 0 1
Example: C = XY 1 0 0 1
1 1 1 0
S = X'Y + XY' = X⊕Y
5) Draw logic diagram.
X
S
Y
Half Adder

C
Gate-level (SSI) Design: Full Adder
 Half-adder adds up only two bits.
 To add two binary numbers, we need to add 3
bits (including the carry).
 Example: 1
0
1
0
1
1 1
carry
X
+ 0 1 1 1 Y
1 0 1 0 S

Need Full Adder (so called as it can be made from two half-
adders).
X
Full S
Y
Z
Adder C
(X + Y + Z)
Gate-level (SSI) Design: Full Adder
 Truth table:
X Y Z C S
Note:
0 0 0 0 0
0 0 1 0 1 Z - carry in (to the current
0 1 0 0 1 position)
0 1 1 1 0 C - carry out (to the next position)
1 0 0 0 1
1 0 1 1 0 C
YZ
1 1 0 1 0 X
00 01 11 10
1 1 1 1 1 0 1

1 1 1 1
Using K-map, simplified SOP form:
C = XY + XZ + YZ S
YZ
S = X'Y'Z + X
00 01 11 10

X'YZ'+XY'Z'+XYZ 0 1 1

1 1 1
Gate-level (SSI) Design: Full Adder
 Alternative formulae using algebraic manipulation:
C = XY + XZ + YZ
= XY + (X + Y)Z
= XY + ((X⊕Y) + XY)Z
= XY + (X⊕Y)Z + XYZ
= XY + (X⊕Y)Z

S = X'Y'Z + X'YZ' + XY'Z' + XYZ

= X'(Y'Z + YZ') + X(Y'Z' + YZ)
= X'(Y⊕Z) + X(Y⊕Z)'
= X⊕(Y⊕Z) or (X⊕Y)⊕Z
Gate-level (SSI) Design: Full Adder
 Circuit for above formulae:
C = XY + (X⊕Y)Z
S = (X⊕Y)⊕Z

(X⊕Y)
X
Y S

(XY)

Z
Full Adder made from two Half-Adders (+ OR gate).
Gate-level (SSI) Design: Full Adder
 Circuit for above formulae:
C = XY + (X⊕Y)Z
Block diagrams.
S = (X⊕Y)⊕Z

X (X⊕Y)
X Sum X
Y Y Sum S
Y
Half Half
Adder Adder
(XY)
Carry Carry
C

Z
Full Adder made from two Half-Adders (+ OR gate).
Code Converters
 Code converters – take an input code, translate to its
equivalent output code.

Input Code Output

code converter code

Example: BCD to Excess-3 Code Converter.

Input: BCD digit
Output: Excess-3 digit
BCD-to-Excess-3 Code Converter
 Truth table: K-maps:
BCD Excess-3 CD C CD C
A 00 01 11 10 A 00 01 11 10
A B C D W X Y Z B B
00 00 1 1 1
0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0 01 1 1 1 01 1
B B
2 0 0 1 0 0 1 0 1 11 X X X X 11 X X X X
3 0 0 1 1 0 1 1 0 A A
10 1 1 X X 10 1 X X
4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0 D D
W X
6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1 CD C CD C
A 00 01 11 10 A 00 01 11 10
9 1 0 0 1 1 1 0 0 B B
00 1 1 00 1 1
10 1 0 1 0 X X X X
11 1 0 1 1 X X X X 01 1 1 01 1 1
B B
12 1 1 0 0 X X X X 11 X X X X 11 X X X X
13 1 1 0 1 X X X X A A
10 1 X X 10 1 X X
14 1 1 1 0 X X X X
15 1 1 1 1 X X X X D D
Y Z
BCD-to-Excess-3 Code Converter
CD C CD C
A 00 01 11 10 A 00 01 11 10
B B
00 00 1 1 1 W = A + BC + BD
01 1 1 1 01 1
B B
11 X X X X 11 X X X X
A
10 1 1 X X
A
10 1 X X X = B'C + B'D + BC'D'

W D X D
Y = CD + C'D'
CD C CD C
A 00 01 11 10 A 00 01 11 10
B
00 1 1 B
00 1 1 Z = D'
01 1 1 01 1 1
B B
11 X X X X 11 X X X X
A A
10 1 X X 10 1 X X

Y D Z D
Block-Level Design Method
 More complex circuits can also be built using block-
level method.
 In general, block-level design method (as opposed to
gate-level design) relies on algorithms or formulae of
the circuit, which are obtained by decomposing the
main problem to sub-problems recursively (until
small enough to be directly solved by blocks of
circuits).
 Simple examples using 4-bit parallel adder as
building blocks:
 (1) BCD-to-Excess-3 Code Conversion
 (2) 16-Bit Parallel Adder
 (3) Adder cum Subtractor
4-bit Parallel Adder
 Consider a circuit to add two 4-bit numbers together
and a carry-in, to produce a 5-bit result:
X4 X3 X2 X1 Y4 Y3 Y2 Y1

4-bit
C5 C1
Parallel Adder

Black-box view of 4-bit

S4 S3 S2 S1 parallel adder

5-bit result is sufficient because the largest result is:

(1111)2+(1111)2+(1)2 = (11111)2
4-bit Parallel Adder
 SSI design technique should not be used.
 Truth table for 9 inputs very big, i.e. 29=512 entries:
X4X3X2X1 Y4Y3Y2Y1 C1 C5 S4S3S2S1
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 0 0 0 0 1
0 0 0 0 0 0 0 1 0 0 0 0 0 1
... ... ... ... ...
0 1 0 1 1 1 0 1 1 1 0 0 1 1
... ... ... ... ...
1 1 1 1 1 1 1 1 1 1 1 1 1 1

Simplification very complicated.

4-bit Parallel Adder
 Alternative design possible.
 Addition formulae for each pair of bits (with carry in),
Ci+1Si = Xi + Yi + Ci
has the same function as a full adder.
Ci+1 = Xi Yi + (Xi ⊕ Yi ) Ci
Si = Xi ⊕ Yi ⊕ Ci
4-bit Parallel Adder
 Cascading 4 full adders via their carries, we get:
Y4 X4 Y3 X3 Y2 X2 Y1 X1
C4 C3 C2

C5 FA FA FA FA C1

S4 S3 S2 S1
Input
Output
Parallel Adders
 Note that carry propagated by cascading the carry
from one full adder to the next.
 Called Parallel Adder because inputs are presented
simultaneously (in parallel). Also, called Ripple-Carry
Adder.
BCD-to-Excess-3 Code Converter
 Excess-3 code can be BCD Excess-3
converted from BCD code 0
A
0
B C
0 0
D
0
W X Y Z
0 0 1 1
using truth table: 1 0 0 0 1 0 1 0 0
2 0 0 1 0 0 1 0 1
3 0 0 1 1 0 1 1 0
Gate-level design can be used 4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0
since only 4 inputs. 6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
However, alternative design 8 1 0 0 0 1 0 1 1
possible. 9
10
1
1
0 0
0 1
1
0
1 1 0 0
X X X X
11 1 0 1 1 X X X X
Use problem-specific formulae: 12 1 1 0 0 X X X X
13 1 1 0 1 X X X X
Excess-3 Code 14 1 1 1 0 X X X X
= BCD Code + 15 1 1 1 1 X X X X
(0011)2
BCD-to-Excess-3 Code Converter
Excess-3 Code = BCD Code + (0011)2
 Block-level circuit: unused

Cout
X4
BCD X3

4-bit Parallel
code X2 S4

Adder
X1 S3 Excess-3
0 Y4 S2 code
0 Y3 S1
1 Y2
1 Y1 Cin
A BCD-to-Excess-3
Code Converter 0
16-bit Parallel Adder
 Larger parallel adders can be built from smaller ones.
 Example: a 16-bit parallel adder can be constructed
from four 4-bit parallel adders:
X16..X13 Y16..Y13 X12..X9 Y12..Y9 X8..X5 Y8..Y5 X4..X1 Y4..Y1
4 4 4 4 4 4 4 4

C17 4-bit // C13 4-bit // C9 4-bit // C5 4-bit // C1

adder adder adder adder
4 4 4 4

S16..S13 S12..S9 S8..S5 S4..S1

A 16-bit parallel adder

16-bit Parallel Adder
 Shortened notation for multiple lines.

4 is a shortened
notation for
S4 .. S1 S4 S3 S2 S1

16-bit parallel adder ripples carry from one 4-bit block to the
next.
Such ripple-carry circuits are “slow” because of long delays
needed to propagate the carries.
4-bit Parallel Adder cum
Subtractor *Optional
 Subtraction can be performed through addition using
2s-complement numbers.
 Hence, we can design a circuit which can perform
both addition and subtraction, using a parallel adder.
X4 X3 X2 X1 Y4 Y3 Y2 Y1

4-bit adder S: control signal

cum subtractor for add/subtract

Result: either X+Y or X-Y

4-bit Parallel Adder cum
Subtractor
 The control signal S=0 means add
S=1 means subtract
 Recall that:
X-Y = X + (-Y)
= X + (2’s complement of Y)
= X + (1’s complement of Y) +1
X+Y = X + (Y)
4-bit Parallel Adder cum
Subtractor
 Design requires:
(i) XOR gates:

Y Y Y Y'
S=0 S=1

such that: output = Y when S=0

= Y' when S=1

(ii) S connected to carry-in.

4-bit Parallel Adder cum
Subtractor
 Adder cum subtractor circuit:
Y4 Y3 Y2 Y1

S
X4 X3 X2 X1

C Cout 4-bit Cin

parallel adder Analysis:
If S=1, then
X + (1's complement of Y) +1
S4 S3 S2 S1 appears as the result.
A 4-bit adder cum subtractor If S=0, then X+Y appears as
the result.
Arithmetic Circuits: Adders
Revision
 Half adder
x y C S Σ
0 0 0 0 X Σ Sum
Input Output
0 1 0 1
bits bits
1 0 0 1 Y Cout Carry
1 1 1 0

x
y' x'
S = xy' + x'y y'
x' S = (C+x'y')'
y x
y C
x
y C

x
y x
S=x⊕ y
S = (x+y)(x'+y') y
x'
y'
C
x
y C
Arithmetic Circuits: Adders
Revision
 Full adder x
0
y
0
z
0
C
0
S
0
Σ
0 0 1 0 1 A Σ Sum
Input Output
0 1 0 0 1 B
0 1 1 1 0 bits Cout Carry bits
Cin
1 0 0 0 1
1 0 1 1 0 yz yz
X' 1 1 0 1 0 00 01 11 10 00 01 11 10
y' x x
z 1 1 1 1 1 0 1 0 1 1
x'
y 1 1 1 1 1
z' 1C = xy + xz + yz 1 + x'yz' + xy'z' + xyz
S S = x'y'z
x
y'
z'
x
y
z x x⊕y
y S = (x⊕y)⊕z
x
xy
y
C = xy + (x⊕y)z
x
z C z
y
z
Arithmetic Circuits: Parallel
Adders Revision
 Example: Adding two 4-bit numbers
Subscript i 4 3 2 1 2 ways:
Input carry 0 1 1 0 Ci
Augend 1 0 1 1 Ai ◆ Serial (one FA)
Addend 0 0 1 1 Bi ◆ Parallel (n FAs for n bits)
Sum 1 1 1 0 Si
Output carry 0 0 1 1 Ci+1
Y4 X4 Y3 X3 Y2 X2 Y1 X1
C4 C3 C2

C5 FA FA FA FA C1

Binary Σ
no. A X 4-bit S4 S3 S2 S1
S sum
Binary
no. B Y
Cout Output carry
Input carry Cin
Arithmetic Circuits: Cascading
Adders Revision
 4-bit parallel adder:
 cascade 4 full adders
 classical method: 9 input variables ➔ 29 = 512 rows in truth
table!

 Cascading method can be extended to larger

numbers, example: 16-bit parallel adder.
X16..X13 Y16..Y13 X12..X9 Y12..Y9 X8..X5 Y8..Y5 X4..X1 Y4..Y1
4 4 4 4 4 4 4 4

C17 4-bit // C13 4-bit // C9 4-bit // C5 4-bit // C1

adder adder adder adder
4 4 4 4

S16..S13 S12..S9 S8..S5 S4..S1

Arithmetic Circuits: Cascading
Adders
 Application: 6-person voting system.
 Use FAs and a 4-bit binary parallel adder.
 Each FA can sum up to 3 votes.

Σ
Voter 1 A Σ 1 Σ
2
Voter 2 B 3 A 1
Cout 4 2
3-bit
Voter 3 Cin S 3 Output
1 4
Full-adder 1 2
B
3
4 Cout
Σ
Cin
Voter 4 A Σ
Parallel adder
Voter 5 B
Cout
Voter 6 Cin

Full-adder 2
Arithmetic Circuits: Adder-
Subtractor Revision
 Make use of 2’s complement:
X - Y = X + (-Y)
 2’s complement of Y = Inverting bits in Y and plus 1.
Y4 Y3 Y2 Y1
S
X4 X3 X2 X1 Zi = S.Yi' + S'.Yi
Z4 Z3 Z2 Z1

4-bit When S=0,

C Cout Cin
parallel adder Cin=0, Zi = Yi ➾ S = X + Y
When S=1,
Cin=1, Zi = Yi' ➾ S = X + Y' + 1
S4 S3 S2 S1
Arithmetic Circuits: Comparator
 Magnitude comparator: compares 2 values A and
B, to see if A>B, A=B or A<B.
 Classical method requires 22n rows in truth table!
 We exploit regularity.
 How do we compare two 4-bit values A (a3a2a1a0)
and B (b3b2b1b0)?
If (a3 > b3) then A > B
If (a3 < b3) then A < B
If (a3 = b3) then if (a2 > b2) ….
Arithmetic Circuits: Comparator
Let A = A3A2A1A0 , B = B3B2B1B0; xi = Ai.Bi + Ai'.Bi'
A3
x3
A3'.B3
A3.B3'
B3
A3'.B3 + x3.A2'.B2
A2
x2 + x3.x2.A1'.B1
B2 + x3. x2.x1.A0'.B0

(A < B)
A1
x1
A3.B3' + x3.A2.B2'
B1
+ x3.x2.A1.B1'
+ x3. x2.x1.A0.B0'
A0
x0 (A > B)
B0
(A = B)
x3. x2.x1.x0
Arithmetic Circuits: Comparator

0 A3 4-bit
1 A2 comp
1 A1
0 A0
1 B3 (A < B) 1
0 B2 (A > B) 0
1 B1 (A = B) 0
0 B0

Block diagram of a 4-bit

magnitude comparator
Propagation Delay
 Every logic gate experiences some delay (though
very small) in propagating signals forward.
 This delay is called Gate (Propagation) Delay.
 Formally, it is the average transition time taken for
the output signal of the gate to change in response to
changes in the input signals.
 Three different propagation delay times associated
with a logic gate:
 tPHL: output changing from the High level to Low level
 tPLH: output changing from the Low level to High level
 tPD=(tPLH + tPHL)/2 (average propagation delay)
Propagation Delay

Input Output

H
Input
L

H
Output
L

tPHL tPLH
Propagation Delay
A B C

 Ideally, no In reality, output signals

delay: normally lag behind input
signals:
1 1
Signal for A Signal for A
0 0

1 1
0 Signal for B 0 Signal for B

1 1
Signal for C Signal for C
0 0
time time
Calculation of Circuit Delays
 Amount of propagation delay per gate depends on:
 (i) gate type (AND, OR, NOT, etc)
 (ii) transistor technology used (TTL,ECL,CMOS etc),
 (iii) miniaturisation (SSI, MSI, LSI, VLSI)

 To simplify matters, one can assume

 (i) an average delay time per gate, or
 (ii) an average delay time per gate-type.

 Propagation delay of logic circuit

= longest time it takes for the input signal(s) to propagate to the
output(s).
= earliest time for output signal(s) to stabilise, given that input
signals are stable at time 0.
Calculation of Circuit Delays
 In general, given a logic gate with delay, t.
t1
t2 Logic
: : Gate
tn max (t1, t2, ..., tn ) + t

If inputs are stable at times t1,t2,..,tn, respectively; then the

earliest time in which the output will be stable is:
max(t1, t2, .., tn) + t

To calculate the delays of all outputs of a combinational

circuit, repeat above rule for all gates.
Calculation of Circuit Delays
 As a simple example, consider the full adder circuit
where all inputs are available at time 0. (Assume
each gate has delay t.)
0 max(0,0)+t = t
X max(t,0)+t = 2t
Y 0
S

t 2t max(t,2t)+t = 3t
C
0
Z

where outputs S and C, experience delays

of 2t and 3t, respectively.
Calculation of Circuit Delays
 More complex example: 4-bits parallel adder.
Y4 X4 Y3 X3 Y2 X2 Y1 X1
C4 C3 C2
0 0 0 0 0 0 0 0

0
C5 FA FA FA FA C1

S4 S3 S2 S1
Calculation of Circuit Delays
 Analyse the delay for the repeated block:
Xi 0 where Xi, Yi are
Full Si stable at 0t, while
0
Yi
mt Adder Ci+1 Ci is assumed to
Ci be stable at mt.
Performing the delay calculation gives:
Xi 0 max(0,0)+t = t
max(t,mt)+t
Yi 0 Si

t max(t,mt)+t
max(t,mt)+2t
Ci+1
mt
Ci
Calculation of Circuit Delays
 Calculating:
When i=1, m=0: S1 = 2t and C2 = 3t.
When i=2, m=3: S2 = 4t and C3 = 5t.
When i=3, m=5: S3 = 6t and C4 = 7t.
When i=4, m=7: S4 = 8t and C5 = 9t.
 In general, an n-bit ripple-carry parallel adder will
experience:
Sn = ((n-1)*2+2)t
Cn+1 = ((n-1)*2+3)t
as their delay times.
 Propagation delay of ripple-carry parallel adders is
proportional to the number of bits it handles.
 Maximum Delay: ((n-1)*2+3)t
Faster Circuits
 Three ways of improving the speed of these circuits:
 (i) Use better technology (e.g. ECL faster than TTL gates),
BUT
(a) faster technology is more expensive, needs more power,
lower-level of integrations.
(b) physical limits (e.g. speed of light, size of atom).
 (ii) Use gate-level designs to two-level circuits! (use sum-
of-products/product-of-sums) BUT
 (a) complicated designs for large circuits.
 (b) product/sum terms need MANY inputs!

 (iii) Use clever look-ahead techniques BUT there are

additional costs (hopefully reasonable).
Look-Ahead Carry Adder*
Not covered.
 Consider the full adder:
Xi Pi where intermediate
Yi Si signals are labelled as
Gi Pi, Gi, and defined as:
Ci+1 Pi = Xi⊕Yi
Ci
Gi = Xi.Yi
The outputs, Ci+1,Si, in terms of Pi ,Gi ,Ci , are:
Si = Pi ⊕ Ci …(1)
Ci+1 = Gi + Pi.Ci …(2)
If you look at equation (2),
Gi = Xi.Yi is a carry generate signal
Pi = Xi ⊕ Yi is a carry propagate signal
Look-Ahead Carry Adder
 For 4-bit ripple-carry adder, the equations to obtain
four carry signals are:
Ci+1 = Gi + Pi.Ci
Ci+2 = Gi+1 + Pi+1.Ci+1
Ci+3 = Gi+2 + Pi+2.Ci+2
Ci+4 = Gi+3 + Pi+3.Ci+3
These formula are deeply Ci
nested, as shown here for Pi
Ci+1
Ci+2: Gi

Pi+1
Ci+2
Gi+1

4-level circuit for Ci+2 = Gi+1 + Pi+1.Ci+1

Look-Ahead Carry Adder
 Nested formula/gates cause ripple-carry propagation
delay.
 Can reduce delay by expanding and flattening the
formula for carries. For example, Ci+2
Ci+2 = Gi+1 + Pi+1.Ci+1
= Gi+1 + Pi+1.(Gi + Pi.Ci )
= Gi+1 + Pi+1.Gi + Pi+1.Pi.Ci
New faster circuit for Ci+2
Ci
Pi
Pi+1
Gi Ci+2
Pi+1
Gi+1
Look-Ahead Carry Adder
 Other carry signals can also be similarly flattened.
Ci+3= Gi+2 + Pi+2Ci+2
= Gi+2 + Pi+2(Gi+1 + Pi+1Gi + Pi+1PiCi)
= Gi+2 + Pi+2Gi+1 + Pi+2Pi+1Gi + Pi+2Pi+1PiCi
Ci+4 = Gi+3 + Pi+3Ci+3
= Gi+3 + Pi+3(Gi+2 + Pi+2Gi+1 + Pi+2Pi+1Gi + Pi+2Pi+1PiCi)
= Gi+3 + Pi+3Gi+2 + Pi+3Pi+2Gi+1 + Pi+3Pi+2Pi+1Gi + Pi+3Pi+2Pi+1PiCi
Notice that formulae gets longer with higher carries.
Also, all carries are two-level “sum-of-products”
expressions, in terms of the generate signals, Gs, the
propagate signals, Ps, and the first carry-in, Ci.
Look-Ahead Carry Adder
 We employ the
look-ahead
formula in this
lookahead-carry
adder circuit:
Look-Ahead Carry Adder
 The 74182 IC chip
allows faster
lookahead adder to be
built.
 Maximum propagation
delay is 4t (t to get
generate & propagate
signals, 2t to get the
carries and t for the
sum signals) where t
is the average gate
delay.
Thank You