SYSTEM ON PROGRAMMANLE CHIP USING SOFT PROCESSOR style CORE Click to edit Master subtitle

Prepared byApoorav Gupta Anirudh Singh Prateek Hansrani

GENERAL DESCRIPTION
OBJECTIVES:
To configure the ALTERA FPGA board with a designed hardware and simulate counting program on the same.

HARDWARE:
ALTERAs STRATIX II EP2S180 FPGA board JTAG cable.

SOFTWARE:
SOPC BUILDER QUARTUS II design suite NIOS II IDE

FPGAS
Semiconductor devices that can be programmed even after

manufacturing. FPGA allow us to - program product features and functions. - adapt to new standards. - reconfigure the hardware for specific applications even after the product has been installed in the field. We can use an FPGA to implement any logical function that an application-specific integrated circuit (ASIC) could perform.

ADVANTAGES OF FPGA
Rapid prototyping. Shorter time to market. The ability to re-program in the field for

debugging.

Lower NRE costs. Long product life cycle to mitigate

obsolescence risk.

 Soft-core means the processor core is not fixed in silicon

SOFT CORE PROCESSORS

and can be targeted to any Altera FPGA family.

These Processors are implemented in VHDL, Verilog,

etc., and downloaded onto FPGA hardware.

Can implement many parallel processors on one FPGA. NIOS II is a configurable Soft-core Processor.

Alteras Nios II Processor

A 32-bit soft core processor from Altera. Full 32-bit instruction set, data path, and address space. 32 general-purpose registers. 32 external interrupt sources. Is a RISC, Harvard Architecture: Simple instructions,

separate data and instruction memories. Programs compiled using C/C++ compilers. Performance up to 250 DMIPS.

Nios II Architecture

DIFFERENT NIOS II CORES

Altera offers the following Nios II cores: Nios II/fThe Nios II/f fast core is designed for fast performance. This core presents the most configuration options for fine-tuning the processors performance. Nios II/sThe Nios II/s standard core is designed for small size while maintaining performance. Nios II/eThe Nios II/e economy core is designed to achieve smallest possible core size. This core has a limited feature set, and many settings are not available.

Implementation Of Nios II
The custom FPGA logic that interacts with

the processor is implemented in Altera Quartus II.

The Avalon Interface bus (common

instruction/data bus) is implemented in Quartus II.

The architecture is generated in Quartus II

and used for programming in Eclipse IDE.

PROGRAMMING THE FPGA BOARD

HARDWARE DEVELOPMENT

SOPC Builder
System on a programmable chip a hardware

development tool. Used for integrating various hardware components together like:

Microprocessors, such as the Nios II processor Timers Serial communication interfaces: UARTS General purpose I/O Digital signal processing (DSP) functions Communications peripherals Interfaces to off-chip devices

Memory controllers Buses and bridges Application-specific standard products (ASSP) Application-specific integrated circuits (ASIC) Processors

Generates .SOPC files in Verilog or VHDL which can be

added to the QUARTUS II project.

SOPC Builder Design Flow

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SOPC builder tool

Steps for generating .ptf file

Start the QUARTUS II software. First step is to make a directory for your project. Select FILE > NEW PROJECT WIZARD and enter the

directory and file name. Start the ALTERAS SOPC BUIDER software. In this required components are selected from a list of various peripherals; they are then integrated by making the node connections. Clock settings base address and IRQ settings can also be altered-SYSTEM > AUTO ASSIGN BASE ADDRESSES SYSTEM > AUTO ASSIGN IRQS.

QUARTUS II
Fully-Integrated Design Tool Multiple Design Entry Methods Logic Synthesis Place & Route Simulation Timing & Power Analysis Device Programming Version Used- V8.1 32-BIT

QUARTUS II Typical CAD design flow:

DESIGN STEP BY QUARTUS

MAKING A (.sof) FILE First a block or schematic diagram for the hardware is

prepared as a .bdf (block diagram file) file in QUARTUS II tool. FILE > NEW > BLOCK DIAGRAM/SCHEMATIC FILE > OK. Block diagrams of peripherals can be selected from SYMBOL TOOLS. Interconnection of blocks is done and a blocks hardware image is made. Input and output pins for the blocks are connected and named specifically.

COMPILATION
v Then PROCESSING >

START > ANALYSIS AND ELABORATION is done. v Pin assignment is done by selecting ASSIGNMENT > ASSIGNMENT EDITOR > PIN. v Thereafter referring to the specification sheet of the board the pins are path, and routed to the pins of the FPGA

Downloading the Hardware

The FPGA configuration file(.sof) is downloaded on the board:Connect the board to the host computer via the USB download cable. Start Quartus II Programmer from NIOS II IDE tools. Click Auto Detect. Click Change File and Browse to the <NIOS II standard design directory> directory and Select the programming file <FPGA programming file>.sof for your board. We can select the hardware as USB Blaster and JTAG through Hardware setup option and change their settings. Turn on the Program/Configure option for the programming file. Click Start.

Continued..
The Progress

meter sweeps to 100% as the Quartus II software configures the FPGA.

When

configuration is complete, the FPGA is configured with the Nios II system, but it does not yet have a C

SOFTWARE DEVELOPMENT

NIOS II IDE

NIOS II IDE
NIOS II IDE build flow is an easy-to-use Graphical User

Interface (GUI) .

The Nios II IDE integrates Text editor Debugger Nios II flash programmer and Quartus II Programmer. Nios II C-to-Hardware (C2H) compiler GUI. Nios II IDE is based on the popular Eclipse IDE framework .

Interrupt Handling
When a button is pressed, an IRQ is

generated.

The generated IRQ of the peripheral interrupts

in the normal program flow.

When an IRQ occurs, ISR (Interrupt Service

Routine) reads it, and return the program to initial stage upon completion.

The button press value is stored in edge

capture register as global variable.

Hardware Abstraction Layer (HAL)

Isolates the application software from hardware

modifications.
Applications are device-independent because they

abstract information from such systems as: Character mode devices: UART core, JTAG UART core, LCD display controller Flash memory devices Timer devices DMA controller core Ethernet MAC/PHY Controller
HAL application program interface (API) is integrated

with the ANSI C standard library.

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Layers of HAL API

HAL library generation: SOPC Builder generates a hardware system Nios II IDE generates a custom HAL system library to match the hardware configuration Changes in the hardware configuration automatically propagate to the HAL device driver configuration NIOS II is programmed in C
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Creating the program

File > New Project wizard selector. Select Nios II C/C++ Application and click Next. Give the name of the project and the location of the SOPC

builder PTF file is specified.

BLANK PROJECT TEMPLATE is selected. Finish.

Run and Debug

Nios II C/C++ Projects tabs and chooses

Build Project. Compilation of the project starts and appears in the Console tab. File > New > Source File. Select New Project in the project tab, choose Run As, and choose Nios II Hardware. The programming is shown in the Nios II IDE Console tab.

OBSERVATIONS
The four "buttons" (SW0-SW3) are used to

control output to these devices in the following manner: Button1 (SW0) => "Up counting Button2 (SW1) => "Down counting" Button3 (SW2) => "Up/Down counting from given data" Button4 (SW3) => "Reset to 0 and wait for user's response".
Upon completion of "counting", there is an

APPLICATIONS
Various applications of FPGAs have been enlisted below: Bridging multiple network protocols to

provide hardware interoperability. Uses network of Radars to increase the warning time for tornadoes, flash floods, and other severe weather disturbances. Uses data acquisition systems, which gather information from Radars.

REFERENCES
HANDBOOKS

1.) NIOS II processor reference handbook. 2.) NIOS II software developer handbook. 3.) QUARTUS II handbook version 8.1. 4.) STRATIX II EP2S180 DSP development board handbook. TUTORIALS 5.) NIOS II IDE tutorials. 6.) QUARTUS II hardware development tutorial. WEB REFERENCES

THANK YOU