8051 Microcontroller

Features Single supply +5 V operation 4 KB program memory on chip 128 bytes RAM on chip Four register banks 64 KB each program and external RAM addressability one s instruction cycle 32 bidirectional I/O lines (Ports 0 to 3) Two 16 bit timers Hardware multiply/divide in 4 s.

8051 Microcontroller
Vss Vcc RST

XTAL1 XTAL2 EA/VDD PSEN ALE RxD TxD INT0 INT1

Port 0 Port 1

8051

Port 2 Port 3

T0 T1

WR RD

Pin Details of 8051

I/O Ports- Four 8 bit ports P0-P3. Upon reset all are configured as O/P ports. To use as I/P should be reprogrammed. XTAL1,XTAL2- Has an on chip oscillator. Requires an external clock to run it. RST-Reset pin. A HIGH will terminate all C activities. EA/VDD- 8051 has on chip ROM/EPROM. This must be connected to Vcc. When no on chip ROM is present this is grounded. (External Access)

Pin Details of 8051

PSEN-Program store enable. When external ROM holds the program this is connected to OE pin of the ROM. ALE- When external memory is used with C, Port 0 provides both address and data. ALE is used to demultiplex address and data. RxD,TxD- Receive and transmit data. INT0,INT1- external interrupt pins. T0,T1- Used with Timers 0 and 1. WR,RD-used with external memories.

Internal Architecture of 8051

ALU A B PSW SFRs & RAM Latch Port 0-3

SP IE
ROM

IP PCON
SBUF SCON Port 0 Port 1 Port 2 Port 3 I/O, AD0-AD7 I/O I/O, A8-A15 I/O, Int,Counter, Serial data,RD,WR TCON TMOD TL0 TH0 TL1 TH1

PC

DPTR

Bank 0 Timing & Control Logic Bank 1 Bank 2

Bank 3
Bit/Byte Address

Internal Architecture of 8051

CPU- This consists of 8 bit ALU and associated registers A,B,PSW,PC,DPTR. Accumulator(A)-8 bit. Holds source operand and receives result in arithmetic operation. Source/Destination for logic operations. B Reg-Used in Mul/Div operations. Can also be used as general purpose register. SP- 8 bit register used for stack DPTR-used as base register in indirect jumps and external data transfer

Internal Architecture of 8051

PSW- CY AC F0 RS1 RS2 OV CY-Carry Flag AC-Auxiliary carry F0-User defined Flag RS1,RS2-select register bank OV- Overflow Flag P-Parity Flag
P

Internal Architecture of 8051

RAM-Consists of 4 register banks and 144 general purpose bits. Organized into 3 areas. 32 bytes from 00H to 1FH makeup 32 working registers organized as 4 banks of 8 regs.(R0-R7 in each bank.). A bit addressable area of 16 bytes occupies area from 20H to 2FH. A general purpose RAM from 30H to 7FH addressable as bytes.

Special Function Register

A-Accumulator B-Arithmetic /General Purpose DPTR-Addressing external memory IE-Interrupt Enable Controller IP-Interrupt Priority P0-P3-I/O Port Latches PSW-Program Status Word SCON-Serial Port Control SBUF-Serial Port Data Buffer SP-Stack Pointer

Special Function Register

TMOD-Timer/Counter Mod control TCON-Timer/Counter Control TL0/TL1-Timer 0/1 Low byte TH0/TH1-Timer 0/1 High byte Internal ROM-4K ROM Address space is 0000H to 0FFFH

Addressing Modes of 8051

Register Addressing-Can access 8 working registers. R0-R7. MOV A, R3 ADD A, R4 Direct Byte Addressing- Can access any location on chip RAM and special function register. MOV A,50H ADD A, 51H

Addressing Modes of 8051

Register Indirect Addressing-R0 and R1 of each register bank can be used as index/pointer reg. MOV A, @R0 MOV A, @R1 Immediate Addressing-Data specified along with instruction. MOV A, #52 Register Specific-Refer to specific register such as A or DPTR. SWAP A

Addressing Modes of 8051

Indexed- Only program memory can be accessed in indexed addressing. Either DPTR or PC can be used as an index register MOVC A, @ A+DPTR

Instruction Set
Instructions can be divided into following groups Data Transfer Arithmetic operations Logical Operations Boolean variable manipulation Program and machine Control Data transfer using DPTR and PC Data bit transfer instructions

Data transfer Instructions

MOV A,Rn MOV A,0F0H MOV A,@R1 MOV A,#52H MOV Rn, A MOV Rn,F5H MOV Rn, #55H MOV Direct, A MOV 48H,A

Data transfer Instructions

MOV Direct, Rn MOV A0H, R3 MOV Direct,Direct MOV 50H,40H MOV Direct, @R0 MOV Direct, #Data MOV @Ri, A MOV @Ri, Direct MOV @Ri, #data MOV DPTR, Data16

Data transfer Instructions

MOVX A, @DPTR-refers to external memory MOVX @DPTR,A MOVX @Ri,A MOVX A, @Ri MOVX A, @A+DPTR MOVC A, @A+PC-refers to code memory PUSH Direct POP Direct

Data transfer Instructions

XCH A,Rn XCH A, Direct XCH A, @Ri XCHD A, @Ri- exchanges lower order nibble

Arithmetic Instructions
ADD A, Rn (A)+(Rn) A ADD A, Direct ADD A, @Ri ADD A, #data8 ADDC A, Rn ADDC A, Direct (A)+(Direct)+CY ADDC A, @Ri ADDC A, #data8

Arithmetic Instructions
SUBB A, Rn A - (Rn+CY) SUBB A, Direct SUBB A, @Ri SUBB A, #data8 INC A (A) + 1 A INC Rn INC Direct INC @Ri INC DPTR A

Arithmetic Instructions
DEC A DEC Rn DEC Direct DEC @ Ri MUL AB (A)*(B) B(MSB)A(LSB) DIV AB A/B A(Quotient) B (Remainder) DAA Must be used after ADD / ADC

Logical Instruction
ANL A, Rn ANL A, Direct ANL A, @Ri ANL A, #Data 8 ANL Direct, A ANL Direct, #Data8 ORL A, Rn ORL A, Direct ORL A, @Ri

Logical Instruction
ORL A, #Data 8 XRL Direct, A XRL Direct,#Data8 CRL A (Clears Accumulator) CPL A (Compliments Contents of A) RL A (Rotate left acc without CY) RLC A (Rotate left acc once thro Carry) RR A (Rotate right ACC without CY) RRC A (Rotate right ACC thro CY) SWAP A (Swaps nibbles of Acc)

Bit Manipulation Instruction

ANL C, 40H (C) AND (40H) (C) ANL C, /Bit ANL C, /50 H (C) AND (50 H) (C) ORL C, bit ORL C, /bit CLR C CLR bit CLR 42H Before [42H]=1 After [42 H]=0

Bit Manipulation Instruction

SETB C SETB bit MOV C, Bit MOV C, 44H (44H) (CY) MOV Bit, C CPL C (Compliment Carry) CPL bit

Branching Instruction
AJMP Addr Absolute jump. PC jumps to location labelled addr within 2K LJMP Addr (jump within 64K) SJMP Reladdr8 (jump to +127/-128 bytes from present position) JMP @A+DPTR ((DPTR)+(A)) PC JZ reladdr8 (jump if A=0) JNZ reladdr8

Branching Instruction
JC reladdr8 JNC reladdr8 JB bit addr, reladdr8 JB 40 H, reladdr 8 if (40H)=1 then branch JNB bit addr, reladdr8 JBC bit addr, reladdr8 (jump if bit =1 and clear the bit in addr) DJNZ Rn, reladdr (Decrement Rn by 1 and jump if not zero) DJNZ Direct, reladdr8 (Decrement contents of addr by 1 and jump if non zero

Branching Instruction
CJNE A, direct byte, reladdr8 Compares 2 byte operands and executes a jump if they disagree ACALL Addr (Unconditional CALL to within 2K locations) LCALL Addr (Unconditional CALL to within 64K locations) RET RETI (used in ISS) NOP

Sample Program
Program to initialise the registers MOV R0, #9A MOV B, #1F MOV DPTR, #4500 MOV A, #20 XCH A, R0 L1: SJMP L1

Sample Program
16 Bit addition Data1:1234 Data2 :5678 Result in 4150 and 4151 CLR C ADDC A,#56 MOV A, #34 MOVX @DPTR, A ADDC A, #78 L1: SJMP L1 MOV DPTR, #4150 MOVX @DPTR, A INC DPTR MOV A, #12

Sample Program
8 bit multiplication Multiply contents of reg A & B and store the result at 4500 & 4501 MOV A,#OA MOV B, #88 MUL AB MOV DPTR, #4500 MOVX @DPTR, A INC DPTR MOV A,B MOVX @DPTR, A L1: SJMP L1

Sample Program
8 bit division MOV A, #65 MOV B, #08 DIV AB MOV DPTR, #4500 MOVX @DPTR, A INC DPTR MOV A,B MOVX @DPTR, A L1:SJMP L1