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AVR
Atmel AVR 8-Bit Processors come in a variety of configurations and packages
They all share a common core registers, instructions, basic I/O capabilities
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ATMega16 Specs
131 Instructions 32 8-bit GP registers Throughput up to 16 MIPS 16K programmable flash (instructions) 512Bytes EEPROM 1K internal SRAM Timers, serial and parallel I/O, ADC
Dr. Tim Margush - Assembly Language Programming 3
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AVR CPU
PC: address of next instruction IR: prefetched instruction ID: current instruction GPR: R0-R31 ALU: Note internal data path
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AVR Memory
Flash: Machine instructions go here SRAM: For runtime data
Note bus independence for data and instructions
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Flash Memory
Programs reside in word addressable flash storage
Word addresses range from 0000-1FFF (PC is 13 bits) Byte addresses range 0000-3FFF (0x4000=16K)
Harvard Architecture
It is possible to use this storage area for constant data as well as instructions, violating the true spirit of this architecture
SRAM
The ATMega16 has 1K (1024 bytes) of byte addressable static RAM
This is used for variable storage and stack space during execution SRAM addresses start at $0060 and go through $045F
The reason for not starting at zero will be covered later
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EEPROM
Electrically Erasable Programmable Read Only Memory
Programs can read or write individual bytes This memory is preserved when power is removed Access is somewhat slow; it serves as a form of secondary storage
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Clock
All processors are pushed through their fetch execute cycle by an alternating 0-1 signal, called a clock The ATMega16 can use an internal or external clock signal
Clock signals are usually generated by an RC oscillator or a crystal
The internal clock is an RC oscillator programmable to 1, 2, 4, or 8 MHz An external clock signal (crystal controlled) can be more precise for time critical applications
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Load Immediate
LDI Rd, K
Load a constant into a register (Rd = K) 1110 bbbb rrrr bbbb
Limitations: 16 <= d <= 31; 0x00 <= K <= 0xFF
LDI Examples
LDI R16, $2C
1110 0010 0000 1100 or 0xE20C
Add Registers
ADD Rd, Rr
Add the contents of two registers, store result in Rd (Rd = Rd + Rr) 0000 11rd dddd rrrr
Any registers: 0 <= r <= 31; 0 <= d <= 31
ADD Examples
ADD R16, R3
ddddd is 10000 and rrrrr is 00011 0000 1101 0000 0011 or 0x0D03
How does the processor "know" where the opcode portion stops?
Expanding Opcodes
LDI: 1110011110110011 ADD: 0000111100101101
Similarly, no prefix of 000011 is an opcode and no opcode longer than 6 begins with this sequence
Except lsl Rd 0000 11dd dddd dddd
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Observe result
R16 has the sum of $2C and $0F, $3B
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AVR Studio
An integrated development environment
Provides a text editor Supports the AVR assembler Supports the gnu C compiler Provides an AVR simulator and debugger Provides programming support for the AVR processors via serial interface
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Location should be a folder to hold all project folders Each project should be in its own folder
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Workspace
Editor
Output
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Start Debugging
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Using Mnemonics
Rather than code the machine language program as a sequence of numeric word values expressed in hexadecimal, assembly language programmers usually use instruction mnemonics
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What's Next?
In our sample program, we executed three instructions, what comes next?
Undefined! Depends on what is in flash
0000: 0001: 0002: 0003: $E20C $E01F $0F01 $???? LDI R16, $2C LDI R17, $0F ADD R16, R17 ???
If a program is to simply stop, add an instruction that jumps to its own address
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Relative Jump
RJMP K 1100 kkkk kkkk kkkk
-2048 <= K < 2048
We want K = -1
This will cause a jump to the address from which the instruction was fetched
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Relative Jump
Here: RJMP Here 1100 kkkk kkkk kkkk
K = -1 ($FFF) 1100 1111 1111 1111 or $CFFF
0000: 0001: 0002: 0003: 0004: $E20C $E01F $0F01 $CFFF $???? LDI R16, $2C LDI R17, $0F ADD R16, R17 RJMP -1 This distance is -1 word ???
Remember that the program counter is incremented before the instruction is executed
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