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For complex processes, it becomes difficult to understand the intricacies of the fabrication process and interpret different photo masks. They act as interface between the circuit designer and the process engineer.
The fundamental unity in the definition of a set of design rules is the minimum line width.
i.e. a design rule stands for the minimum mask dimension that can be safely transferred the semiconductor material. Even for the same minimum dimension, design rules differ from company to company and from process to process.
However, there are CAD tools that allow the migration of the design between compatible process.
For complex processes, it becomes difficult to understand the intricacies of the fabrication process and interpret different photo masks. They act as interface between the circuit designer and the process engineer.
Design Rules:
N- Well
r101 r102 r110 Minimum width Between wells Minimum well Area 12 12 144 2
r 101
r 102
NWell
r201
r 201
P+ Diff
NWell
r 201
N+ Diff
r202
r 202
P+ Diff
NWell
r 202
N+ Diff
r203
r 203 P+ Diff
r 203
NWell
N+ Diff
r204
P+ Diff
NWell r 204
N+ Diff
r210
162
r 210
P+ Diff
NWell
r 210
N+ Diff
r301
Polysilicon Width
Polysilicon r 301
P+ Diff
N+ Diff
r302
Polysilicon
r 302 P+ Diff
NWell Polysilicon
r 302 N+ Diff
r307
Polysilicon r 307
N+ Diff r 307
r304
Polysilicon
r 304 P+ Diff
NWell Polysilicon
r 304 N+ Diff
r307
Polysilicon
r 307
r 307
P+ Diff
NWell Polysilicon
r 307
r 307 N+ Diff
r401
Contact width 2
Contact r 401
Polysilicon Contact
Metal/Polysilicon Contact
r404
Contact
r 404
Metal/Polysilicon Contact
r405
Contact
Polysilicon Contact
Metal/Polysilicon Contact
r 405
r 405
r403
Polysilicon r 403
P+ Diff
N+ Diff
r501
Metal 1
r 501
Metal 4
Metal 5
Metal 6
r510
Metal 1
r 510 r 510
Metal 4
Metal 5
Metal 6
GATE EXTENSION:
It is necessary for the poly to completely cross active, other wise the transistor that has been created crossing of diffusion and poly, will be shorted by diffused path of source and drain.
NAND2 layout
NOR2 layout
Ordering of polysilicon gate columns in Euler graph sequence results in uninterrupted p-type and n-type diffusion areas. Adv: Compact area, simple routing of signals and less parasitic capacitance.
STICK DIAGRAMS
CONCEPT
Popular Way Of symbolic design. Free hand layout
Notation gives only relative position of various design components. A compactor is used to convert it into absolute design.
Concept
The compactor translates design rules into constraints on the component positions. It also gives optimized design layout with efforts for minimization of area and cost function.
Outcome of the compactor may be unpredictable and may not match manual approach.
Stick diagram layout of the complex CMOS logic gate with arbitrary ordering of poly gate columns.
Ordering of polysilicon gate columns in Euler graph sequence results in uninterrupted p-type and n-type diffusion areas. Adv: Compact area, simple routing of signals and less parasitic capacitance.
E-D-A-B-C
Ex: 1.
Ex: 2.
Ex: 3.
Effect Of Restructuring
Sketch a stick diagram for a combinational circuit evaluating following Boolean expression.