SYNTHESIS AND PHYSICAL DESIGN.

V. RAGHAVA THEJ DEEP

SYNTHESIS.
y In electronics, synthesis is a process by which an

abstract form of desired circuit behavior, typically register transfer level (RTL), is turned into a design implementation in terms of logic gates. Common examples of this process include synthesis of HDLs, including VHDL and Verilog. y Synthesis is next stage to functional design and verification of digital system. y Refinement of functional design to gate-level net list. y For most designs, synthesis is performed automatically using RTL synthesis tool.

y For complex ASIC design with high performance

requirements, it may be necessary to custom design the circuitry of some subsystems. y RTL synthesis ,as name suggests,starts with models of design refined to the register-transfer level. y Hence, cannot use all of the features of HDL(VHDL or Verilog) arbitrarily. y Many language features are suitable for writing testbenches, and cannot be synthesized in equivalent gate-level circuits.

HISTORY
y Early tools-Simple pattern recognition. y Focus more on improving the quality. y Optimization.

Types of standard coding styles

y Different synthesis tools accept different subsets of

input language. y Types: 

VHDL(IEEE Standard 1076.6) Verilog(IEEE Standard 1364.1)

y Initial version of VHDL(1999 and 2002)defined a

subst that was portable across number of tools. y VHDL(2004) extended subset to include more constructs.

Technology library
y Collection of components that are available within

the implementation fabric selected for design. y In ASIC, provided as part of larger design. y In FPGA, embedded in the tools provided by vendors. y Typical Components-inverting ,non-inverting gates, small number of inputs, small multiplexers, carry chain components, flip-flops.

Why perform gate-level simulation?

y Synthesis is followed by a further verification step. y To ensure design meets functional requirements. y Reason for simulation: Technology library includes estimation of timing

parameters of components.  There are ways in which we can write RTL model code that produce different behavior in RTL simulation and synthesis.

Objective of Synthesis
y Minimize area


in terms of literal count, cell count, register count, etc. in terms of switching activity in individual gates, deactivated circuit blocks, etc. in terms of maximal clock frequency of synchronous systems, throughput for asynchronous systems combined with different weights formulated as a constraint problem minimize area for a clock speed > 300MHz feedback from layout actual physical sizes, delays, placement and routing.

y Minimize power


y Maximize performance


y Any combination of the above

 

y More global objectives



PHYSICAL DESIGN.
y Physical design converts a circuit description into a

geometric description. This description is used to manufacture a chip(ASIC and FPGA). y The physical design cycle consists of 1. Partitioning 2. Floorplanning and Placement 3. Routing 4. Compaction
y Final stage in Design flow.

VLSI Design
Specification Physical Design Partitioning

Architectural design Logic design Circuit design Physical design

Placement

Routing Test/Fabrication

Design flow

FLOORPLANNING
y Layout design done at the chip level  Defining layout hierarchy  Estimation of required design area y A blueprint showing the placement of major components in the

design (non-standard cell)  Inputs / Output (I/O)  RAMs / ROMs/  Reusable Intellectual Property (IP) macros
y   

Approaches to Floorplanning (Automatic or Manual) Constructive Iterative Knowledge-Based

y Floorplan of design:

Core area defined with large macros placed Periphery area defined with I/O macros placed Power and Ground Grid (Rings and Straps) established y Utilization: The percentage of the core that is used by placed standard cells and macros Goal of 100%, typically 8085%

Guidelines for a Good Floorplan

PLACEMENT AND ROUTING

y Routing is a fundamental step in the place and route

process y Create metal shapes that meet the requirements of a fabrication process  The physical connection between cells in the design y Virtual routes used during placement and CTS need to become reality  Timing of design needs to be preserved  Timing data such as signal transitions and clock skew needs to match the virtual route estimates

Concept of Place and Route

y Location of all standard

cells is automatically chosen by the tool during placement (Based upon routing and timing) y Pins are physically connected during routing (Based upon timing)

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