Professional Documents
Culture Documents
Eugenio Di Gioia
1
Modeled as voltage source in series with the gate Inversely proportional to the frequency (important al low frequencies) Inversely proportional to the MOS area (large transistors have less Flicker noise) Inversely proportional to the specific capacitance COX It is caused from charge carriers trapped at the interface between silicon and oxide or fluctuation in the mobility of the charge carriers k is process-depending (about 10-25 V2F)+
COX ! I OX tOX [ F/m 2 ]
2
k V 2 / Hz WLCox f
?A
/ Hz
Modeled as current source in parallel between drain and source It is due to the resistive channel Its spectrum is white (the same at all frequencies) is about 2/3 2 I n ( f ) ! 4kTKg dso The exact formula is but for long-channel transistors it is: g m $ g dso
3
Noisy MOS
k V ! WLCox f
2 g 2 I n ( f ) ! 4kTKg m
Thermal
Flicker
2 kg m I ( f ) ! 4kTKg m WLCox f 2 n
Output-referred
Vn2 ( f ) !
4kTK k gm WLCox f
Input-referred
The input-equivalent noise current source was neglected
4
Vout
2 kg m 2 I n ( f ) ! 4kTKg m WLCox f
?V /HzA
2
Vn2,in ( f ) !
Vn2,out ( f ) g R
2 m 2 out
Rout ! RL // r0
5
r0 ! r0 p // r0 n
r ?V /HzA
2 o 2
Vn2,in ( f ) !
Vn2,out ( f ) g r
2 2 m1 o
4kTK (f)! g m1
gm2 g 2 1 ! vn1,in ( f )1 m 2 g m1 g m1
W 2/L2 should be small. By keeping the current constant this increases Vov2 (reduction of the output swing)
If gm1=gm2
2 n ,in
( f ) ! 2v
2 n1,in
(f)
7
Cascode amplifier
Vbias Vin
2 vn1 2 vn 2
I0 Vout
M2
4kTK M2 is source degenerated through ro1 v (f)! g m 2 Gain form G2 to output: AV2=-ROUT/r01
2 n2
r01
M1
2 vn1 ( f ) !
4kTK g m1
4kTK 2 2 g m1ROUT g m1
2 n ,in
1 1 g g r2 m 2 m1 01
Cascode amplifier
Vbias Vin
2 vn1 2 vn 2
I0 Vout
M2
r01
M1
2 in ,out
Only M1 is noisy
2 vn 2
4kT RL
M2
Vout
2 n ,in
(f)!
2 vn ,out ( f ) 2 2 g m1 ROUT
4kTK ! g m1
M1
4kT 1 1 g g r2 R g2 m 2 m1 01 L m1
M1
M2
RL
2 n ,in
4kT (f)! g m1
K 1 2 K $ vn1,in ( f ) 2 2 g m 2 g m1r01 RL g m1
10
Active Cascode
RL
M2
2 I nRL ( f ) !
v Vin
2 n2
4kT RL
Vout A3
2 vn 3
M1
2 n1
2 n ,in
4kT (f)! g m1
Folded Cascode
2 vn 3
M3 v
2 n1
2 vn 2
4kTK v (f)! g mi
2 ni
M1
M2
RL
2 n ,out
(f)!v g R
2 n1 2 m1
2 out
Gain G1/output
Gain G2/output
Gain G3/output
2 n ,out 2 2 m1 out
2 n2
2 n3
2 m3
R1
vin
R2 vout
M2
vin
Noise analysis:
The noise contribution of M3 can be neglected (symmetry) For noise analysis node X is not virtual ground! (uncorrelated sources)
M1
VBIAS
M3
13
R1
M1
2 iR1
2 iR 2
R2
2 vn 2
v
2 in1
2 n ,out 2 in 2
M2
2 n1
f ! 4kTKg m1
2 n2
f
! 4kTKg m 2 ! i f
2 n1
4kT i f
! R1
2 R1
2 iR 2 f !
4kT 2 ! i R1 f R2
Superposition principle: all uncorrelated noise sources are considered separately. The output noise power will be added.
14
R1
M1
in1 / 2
in1 / 2
R2
M2
vn ,out
in1 / 2
in1
1/ gm
1/ gm
in1 i R1 n1 R2 ! in1 R1 2 2
vn1,out f !
15
R1
M1
inR1
ix $ 0
inR1
2 vn ,out
R2
M2
vnR1,out ! inR1 R1
2 vnR1,out ! 4kTR1
16
Noise of Resistor R2
Because of the symmetry:
2 2 vnR 2,out ! vnR1,out ! 4kTR1
2 vn ,in
Input-referred noise power is doubled compared to single ended Common-Source Input signal power is four times larger SNR is improved by +3 dB
17
M2
2 vn1
Two-stage OTA
M3
Total transconductance:
IN
M1
2 vn 3
Gm ! g m1 r01 // r02 g m3
2 2 2 vn ,in ( f ) ! vn1 vn 2
M1
M2
2 2 vn ,in ( f ) $ 2vn1
M3
18
M3
IB
IN
M1
1: B
OUT
Low-voltage suitable Transconductance (but not voltage gain) is larger than standard single stage but smaller than two-stage OTA: Gm ! g m1 B
1 r0 w ID
B =2 to 4
19
M2
2 vn1
M3
2 2 2 vn ,in ( f ) ! vn1 vn 2
2 2 gm2 gm2 2 vn 3 2 2 g m1 g m1
OUT
M1
IN
1: B
v
g m1 $ g m 2 g m 3 ! Bg m 2
2 n ,in
2 n ,in
4kTK 1 (f)! 1 1 g m1 B
20
AI B
M2
IB
IN
M1
1: B
OUT
Compromise between singlestage and two-stage Low-voltage suitable Transconductance and voltage gain are larger than single stage
Gm ! g m1 B
A 0.8-V, 8- W, CMOS OTA with 50-dB Gain and 1.2-MHz GBWin 18-pF Load L. Yao, M. Steyaert and W. Sansen
1 A
I B
AI B
M2
2 vn 2
2 vn3
M3
g m 2 ! g m1 A 1 g m3 ! Bg m 2 ! B A g m1 1 g m 4 ! g m1 A
1: B IN
2 n1
IB
M1
OUT
4kTK 1 v (f)! w g mi g mi
2 ni
1 A
I B
AI B
M2
2 n2
2 n3
Gain G4/Input
M3
2 2 2 2 vn ,in ( f ) ! vn1 vn 2 vn 3
2 2 g m2 gm4 2 vn 4 2 2 g m1 g m1
1: B IN
2 n1
IB
M1
OUT
Gain G2/input
2 2 2 2 2 vn ,in ( f ) ! vn1 vn 2 vn 3 A vn 4 A2 1
1 A ( f ) ! v 1 A
1 A B
2 n1 23
1 A ( f ) ! v 1 A
1 A B
2 n1
2 n ,in
1 A ( f ) ! v 2 B
2 n1
2 vn ,in ( f ) !
4kTK g m1
1 A 2 B
24
Cf
I n1
I nf
I n
Vin
Rf Vout
Rf Vout I n
Vin R1 Vn
R2
Vn 2 R2
Integration impedance
! I
2 n1
f
I f
I f
AZ f f
2 nf 2 n
26
! I
2 n1
f
I f
I f
AZ f f
2 nf 2 n
! I
2 n1
f
I f
I f
A
2 nf 2 n
Rf
R f j[C f 1
3-dB frequency
f 3dB !
1 2TR f C f
27
! I
2 n
f R
2 2
V
2 n2
f
V f
AA f
2 n
A f ! 1
Zf R1 R f / R1 !
A f ! 1
1 j[R f C f R f / R1 1 j[R f C f
28
1 j[R f C f
1 sP ! Rf C f
sN !
2 no 2
! I
2 n
f R
2 2
V
2 n2
f
V f
A 1
2 n
R f / R1 1 j[R f C f
29
10
10
10
10
10
30
Frequenc y (r ad/s ec )
31
AR
Rf
f
j[C f 1
Seite 27
fr f=0
2 2 2 2 Vno1 ! I n1 f
I nf f
I n f
R f ! 147 nV/ Hz
Vno1 ! 147nV/ Hz
2 2 2 Vno 2 ! I n f
R2 Vn22 f
Vn2 f
1
R f / R1 1 j[R f C f Rf R1
2
Seite 29
fr f=0
2 no 2
! I
2 n
f R
2 2
V
2 n2
f
V f
A 1
2 n
! 265nV/ Hz
Vno 2 ! 265nV/ Hz
32
The End
33