Professional Documents
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International Workshop on The Future of Nano Electronics Research and Challenges Ahead
International Students
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Total 982
(As of May. 1, 2005)
Cathode (heated)
Grid
st Computer Eniac: made of huge number of vacuum tubes 19 Big size, huge power, short life time filament
dreamed of replacing vacuum tube with solid-state device Today's pocket PC made of semiconductor has much higher performance with extremely low power consumption
J. E. LILIENFELD
DEVICES FOR CONTROLLED ELECTRIC CURRENT
J.E.LILIENFELD
Negative bias
No current
Electron
Positive bias
Electric field
10
Current flows
Mechanism of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) G Surface Gate electrode
Gate Oxd Channel
Source
Drain
S Electron flow
0V N+-Si
Source
Channel
1V N-Si Drain
However, no one could realize MOSFET operation for more than 30 years. Because of very bad interface property between the semiconductor and gate insulator Even Shockley!
12
Very bad interface property between the semiconductor and gate insulator Interfacial Charges
GeO Ge
e
Electric Shielding
Carrier Scattering
Even Shockley!
13
However, they found amplification phenomenon when investigating Ge surface when putting needles. This is the 1st Transistor: Not Field Effect Transistor, But Bipolar Transistor (another mechanism)
J. Bardeen
W. Bratten,
Bipolar using Ge
W. Shockley
14
Top View
Si e rc ou S in ra D Si
te a lG A
Al SiO2 Si Si/SiO2
Interface is 15 exceptionally
4bit MPU
Intel 4004
16
17
1T = 1012 = Trillion
World Population 7 Billion Brain Cell 10 100 Billion Stars in Galaxy 100 Billion
18
19
2.4cm X 3.2cm X 0.21cm Volume 1. 6cm Weight 2g Voltage 2.7 - 3.6V Old Vacuum Tube 5cm X 5cm X 10cm, 100g,100W 1Tbit = 10k X10k X 10k bit Volume = 0.5km X 0.5km X 1km = 0.25 km3 = 0.25X1012cm3 Weight = 0.1 kgX1012 = 0.1X109ton = 100 M ton Power = 0.1kWX1012=50 TW Supply Capability of Tokyo Electric Power Company: 55 BW
20
Downsizing of the components has been the driving force for circuit evolution
1900 1950 1960 1970 LSI 10 m 10-5m 2000 ULSI 100 nm 10-7m Vacuum Transistor IC Tube 10 cm cm mm 10 m
-1
10 m
-2
10-3m
In 100 years, the size reduced by one million times. There have been many devices from stone age. We have never experienced such a tremendous reduction of devices in human history.
22
nsizing Reduce Capacitance Reduce switching time of MOSFETs Increase clock frequency Increase circuit operation speed Increase number of Transistors Parallel processing Increase circuit operation speed
Downsizing contribute to the performance increase in double ways
Many people wanted to say about the limit. Past predictions were not correct!! Expected Period Cause
limit(size)
Late 1970s 1m: Early 1980s 0.5m: arly 1980s 0.25m: ate 1980s 0.1m: 50nm: 10nm:
2000
000
Historically, many predictions of the limit of downsizing. VLSI text book written 1979 predict that 0.25 micro-meter would be the limit
VLSI textbook
Finally, there appears to be a 10 fundamental limit of approximately quarter micron channel length, where certain physical effects such as the tunneling through the gate oxide ..... begin to make the devices of smaller dimension unworkable.
27
Direct-tunneling effect
Gate Oxide Si Gate Substrate Electrode Potential Barrier
Wave function Direct tunneling current
G Gate Oxide
Direct tunneling leakage current start to flow when 28 the thickness is 3 nm.
Lg G S D
Lg = 5 m
Lg = 0.1m
Vg = 2.0V 0.02 1.5 V 0.01 1.0 V Id (mA / m) 0.00 0.5 V 0.01 0.00 0.02 0.5 V 0.0 V 0.0 0.04 1.0 V 0.1 0.06 1.5 V 0.2 0.3
Vg = 2.0V
1.5 V 1.0 V
0.5 V
0.0 V
0.0 V
0.0 V
Vd (V)
Vd (V)
Vd (V)
Vd (V)
29
G S D
Gate leakage: Ig Gate Area Gate length (Lg) Drain current: Id 1/Gate length (Lg) Lg small, Then, Ig small, Id large,
Lg = 10 m
0.03 Vg = 2.0V 0.08
Ig Id
Lg = 5 m
Vg = 2.0V
Lg = 0.1m
Vg = 2.0V
Id
Id (mA / m)
0.06
0.04
0.02
0.00
30
Vd (V)
Vd (V)
Vd (V)
Vd (V)
Never Give Up! No one knows future! There would be a solution! Think, Think, and Think! Or, Wait the time! Some one will think for you
31
Surface
Source
Drain
0V N+-Si
Negative P-Si
Tunneling
3nm
Source Channel
1V N-Si Drain
34
Prediction now!
Limitation for MOSFET operation
Tunneling distance 3 nm
Lg = Sub-3 nm?
Below this, no one knows future!
In 40 years: 18 generations, Now 0.7 times per 3 years Size 1/300, Area 1/100,000
Future
However, very difficult and big challenge! Remember MOSFET had not been realized without Si/SiO2!
39
ength of 18 Si atoms
In 40 years: 18 generations, Now 0.7 times per 3 years Size 1/300, Area 1/100,000
Future
(28nm) 22nm 16nm 11.5 nm 8nm 5.5nm? 4nm? 2.9 nm? At least 4,5 generations to 8nm Hopefully 8 generations to 3nm
Subthreshould Leakage Current Ioff Vg=0V Subthreshold region Vth (Threshold Voltage) Vg
43
10-3A 10-4A 10-5A 10-6A 10-7A 10-8A 10-9A 10-10A Vdd=0.5V Vdd=1.5V Vth down-scaling Vth = 300mV Vth = 100mV Vg = 0V Vg (V) Vdd down-scaling
44
44
Subthreshold Current Is OK at Single Tr. level But not OK For Billions of Trs.
45
10
The down scaling of MOSFETs is still possible for at least another 10 years! 3 important technological items for down scaling. New materials 1. Thinning of high-k gate oxide thickness beyond 0.5 nm 2. Metal S/D New structures 3. Wire channel
Candidates
Si + MOX M + SiO2 L B Si + MO MSi + SiO X X 2 e Si + MO M + MSi O i Mg X X Y Na
H
Unstable at Si interface
Radio B C N
Al Si P S Cl Ar Br I At
HfO2 based dielectrics are selected as the active first generation He materials, because of their merit in O F Ne 1) band-offset, 2) dielectric constant 3) thermal stability
Ca Sc Cr MnFc Co Ni Cu Zn Ga Ge As Se K Ti V Sr Y Zr Nb Mo Tc Ru Rb Pd Ag Cd In Sn Sb Te Rh Hf Cs Ba Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po Fr Ra Rf Ha Sg Ns Hs Mt
Kr Xe Rn
LaCePrNdPm EuGdTbDyHoErTmY Lu Sm
La2O3 based dielectrics are thought to be the next generation materials, which may not need a thicker interfacial layer
Ac Th Pa U Np Pu AmCmBk Cf Es FmMdNo Lr
R. Hauser, IEDM Short Course, 1999 Hubbard and Schlom, J Mater Res 11 2757 (1996)
49
i2O
4 2 0 - 2 - 4 - 6 0 1 0 2 0 3 0 4 0 5 0 D i e l e c t r i c C o n s t a n t
XPS measurement by Prof. T. Hattori, INFOS 2003
50
Band offset
High-k gate insulator MOSFETs for Intel: EOT=1nm HfO2 based high-k
PMOS
51
(S ca l
in g
For the past 45 years SiO2 and SiON For gate insulator
Metal
SiO2/SiON
Metal
HfO2 SiO2/SiON
Si
0.5 0.7nm
Lg
EOT can be reduced further beyond 0.5 nm by using direct contact to Si By choosing appropriate materials and processes.
3
45nm node
Si Introduction of High-k
Now
Year
52
Intensity (a.u)
W HfO2k=16 SiOx-IL
1846
1843
1840
1837
k=4
Phase separator
SiOx-IL is formed after annealing 54 Oxygen control is required for optimizing the reaction
W La2O3
Intensity (a.u)
300 oC
k=23
La-silicate
500 oC
k=8~14
1 nm
1843 1840 1837
La2O3 + Si + nO2 Binding energy (eV) La2SiO5, La2Si2O7, La9.33Si6O26, La10(SiO4)6O3, 55 etc. La2O3 can achieve direct contact of high-k/Si
1846
HfO2
La2O3
La2O3 Nd2O3 Pr2O3 PrSiO PrTiO SiON/SiN Sm2O3 SrTiO3 Ta2O5 TiO2 ZrO2(N) ZrSiO ZrAlO(N)
56
EOT=0.37nm
EOT=0.37nm
3.5E-03 3.0E-03
EOT=0.40nm
3.5E-03
EOT=0.48nm
3.5E-03
Vth=-0.06V3.0E-03
2.5E-03 2.0E-03 1.5E-03 1.0E-03 5.0E-04 0.0E+00
Vth=-0.05V 3.0E-03
2.5E-03 2.0E-03 1.5E-03 1.0E-03 5.0E-04 0.0E+00 0.8 10
Vth=-0.04V
Id (V)
0.8
10
0.2
0.4
0.6
0.2
0.4
0.6
0.8
Vd (V)
Vd (V)
Vd (V)
57
However, high-temperature anneal is necessary for the good interfacial property FGA500oC 30min
2
FGA700oC 30min
1.5
FGA800oC 30min
2
20 x 20m
20 x 20m
20 x 20m
Capacitance [F/cm ]
Capacitance [F/cm ]
1.5
Capacitance [F/cm ]
1.5
0.5
0.5
0.5
0 -1
0 -1.5
0.5
0 -1.5
0.5
A fairly nice La-silicate/Si interface can be obtained with high temperature annealing. (800oC)
58
metal La2O3
Si Si
metal La-silicate
Si sub.
Si sub.
Si sub.
Pulse input
500
10
-6
Universal
10
-7
10
-8
EOT~1.3nm
100 0 0
10
-9
T = 300K 16 -3 Nsub = 3 x 10 cm
0.2 0.4 0.6 Eeff [MV/cm] 0.8 1
10 Frequency [Hz]
10
EOT=0.71nm
10 10 10
-3 -4 -5 -6 -7 -8 -9
EOT=1.02nm
L / W = 20 / 20m
Vds = 0.05V
10 10 10 10 10 10 10
EOT=1.63nm
65~70mV/dec
EOT = 0.71nm EOT = 1.02nm EOT = 1.63nm L / W = 2.5 / 50m
-1 -0.5 0 Vg - Vth [V] 0.5 1
W La-silicate
at 1MHz
0 -1 -0.5 0 0.5 Gate Voltage [V] 1
Si sub.
Increasing EOT caused by high temperature annealing can be dramatically suppressed by Silicon masked stacks
61
La2O3
W
MG HK
TiN/W
Si/TiN/W MIPS
Si
2nm
2nm
2nm
Kav ~ 8
Kav ~ 12
Kav ~ 16
200
150
EOT=0.62nm
100
EOT=0.62nm
T = 300K 16 -3 Nsub = 3 x 10 cm L / W = 10 / 10m
No frequency dispersion
50
-0.5
0.5
1 Eeff [MV/cm]
1.5
10 10
300
ITRS requirements
at 1MV/cm
250 200 150 100 50
Jg at Vg = 1V [A/cm ]
10 10 10
T = 300K
10 10
-1
MIPS Stacks
A = 10 x 10m
0.55 0.6 0.65 0.7 EOT [nm] 0.75
2
-2
0.5
0.8
(a)
Extreme scaling in MOSFET mask
Dopant Conc.
(b)
Hard
Lphy Gate
n+-Si
(b)
Gate Source
Drain
n+-Si
y position Channel
Metal Conc.
Gate - Atomically abrupt junction - Lowering S/D resistances - Low temperature process fortal Me S/D
Metal
Lphy = Leff
Gate
Schottky Barrier FET is a strong Metal candidate for textremely scaled n Me al MOSFET
Metal Silicide
Metal Silicide
y position Channel D
67
Bn = ~0.57 eV
Ni silicide/Si diodes
Specification for metal silicide S/D - Atomically flat interface with smooth surface - Suppressed leakage current - Stability of silicide phase and interface in a wide process temperature 68
Ni-silicide
Deposition of Ni film
Rough interface
Si substrate
Annealing
Si substrate
Ni-silicide
Si substrate
Annealing
Si substrate
STI
rough
500nm
flat
500nm
Ni source
STI rough
500nm
flat
500nm
NiSi2 source
STI rough
500nm
flat
500nm
Ni source
10-2
RTA oC, 1min 500 Source Bn (eV) Ni 0.676 0.659 NiSi2 Ni n 1.08 1.00
Si substrate Al contact
10-3
NiSi2 source
Si substrate Al contact Schottky diode structures
10-4 NiSi2 10-5 -0.8 -0.6 -0.4 -0.2 0.0 Applied Voltage (V) Diode voltage (V) 0.2
NiSi2 source
71
Wire channel
0V
0V
Planar
Surrounding gate
73
W dep
Leakage current
1 V
Planar FET
Fin FET
Nanowire FET
G
Fin Tri-gate -gate All-around 75
Si nanowire FET as a strong candidate 1. Compatibility with current CMOS process 2. Good controllability of IOFF
1
D
W dep
Leakage current
Off cut-off
Source drain
Drain source
1D ballistic conduction
76
Eg
Eg
77
Device fabrication
( )
Si/Si0.8Ge0.2 superlattice epitaxy on SOI
SiN HM
SiN SiN SiGe SiGe Si Si SiGe SiGe Si Si SiGe SiGe Si Si BOX BOX BOX BOX BOX BOX
Gate
Cross-section SiN HM
Drain Gate
500 nm
Wire direction : <110> 50 NWs in parallel 3 levels vertically-stacked Total array of 150 wires EOT ~2.6 nm
C. Dupre et al., IEDM Tech. Dig., p.749, 2008
30nm
Gate Oxidation & Poly-Si Deposition Gate Lithography & RIE Etching Gate Sidewall Formation Ni SALISIDE Process (Ni 9nm / TiN 10nm) Backend Standard recipe for gate stack formation
Recent results to be presented by ESSDERC 2010 next week in Sevile Wire cross-section: 20 nm X 10 nm
60
6.E-05
7.E-05 70
(a)
Vg-Vth=1.0 V
(b) Vd=-1V
20 0
2.E-05
1.E-05 10 0.E+00
0.5
1.0
On/Off>106 60uA/wire
Bench Mark
102A (10x20)
nMOS pMOS
VDD: 1.0~1.5 V
(12x19) (13x20)
Our Work
ION (A / wire)
(12) (12)
(9x14)
70 60 50
(5) (10) (10) (3) (3) (30) (19)
40 30
hi T
Lg=500 65nm
k or w
1.2 1.3V Si nanowireFET Y. Jiang, VLSI 2008, p.34 H.-S. Wong, VLSI 2009, p.92 S. Bangsaruntip, IEDM 2009, p.297 C. Dupre, IEDM 2008, p. 749 S.D.Suk, IEDM 2005, p.735 G.Bidel, VLSI 2009, p.240
Electron Density
4 3 2 1 0
D istance fromS WS iN urface (nm )
Flat portion
Primitive estimation !
Compact model
12000 10000 8000 6000 4000
EOT Small EOT for high-k (33) pMOS P-MOS improvement (26)
Low S/D resistance S/D
ION (A/m)
1m/1m # of wires
Na no wi re
Assumption ION
IONLg-0.5 Tox-1 MG
2000 0 2008
bulk
2012 2014
FD
ITRS
2018 2020 2022
2010
2016
Year
2024
2026
Current Issues Si Nanowire Control of wire surface property Source Drain contact Optimization of wire diameter Compact I-V model III-V & Ge Nanowire High-k gate insulator Wire formation technique CNT: Growth and integration of CNT Width and Chirality control
Chirality determines conduction types: metal or semiconductor
Graphene: Graphene formation technique Suppression of off-current Very small bandgap or no bandgap (semi-metal) Control of ribbon edge structure which affects bandgap 87
88