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Microcontrollers Click to edit Master subtitle style Texas Instruments

MSP430

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Outline
MSP430: An Introduction The MSP430 family Technology Roadmap Typical Applications The MSP430 Documentation MSP430 Architecture MSP430 Devices Getting Started with EasyWeb2

The MSP430 is described as a RISC 3/27/12 processor. utilizing von Neumann architecture.

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Ultra low power

vActive Mode (AM): 300 vLPM0: 85 vLPM3: 1 v LPM4: 0.1

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Popular TI Microcontroller Low Cost Portable USB Interface

Superior

Development
Software

For

Students

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Aging RS232 Interface CISC Architecture Lots of instructions

TI MSP430 Freescale Commonplace USB Interface

RISC Architecture Few Instructions

Windows Style Visual Text Based Development Development Why Switch? Interface Interface

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Features
The ability to use different addressing modes for both source and destination is referred to as instruction orthogonality. The MSP430 is considered to be fully orthogonal, since any instruction can effectively use any addressing mode for both source and destination operands. It allows the programmer to write very compact code.

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Features

Ultralow-power architecture extends battery life 0.1-A RAM retention 0.8-A real-time clock mode 250-A / MIPS active analog ideal for precision measurement or 10-bit ADC 200 ksps,

High-performance 12-bit

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Features
16-bit

RISC CPU enables new applications at a fraction of the code size. register file eliminates working file bottleneck Compact core design reduces power consumption and cost for modern high-level programming

Large

Optimized

The CPU features

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Orthogonal architecture with every instruction usable with every addressing mode. Full register access including program counter, status registers, and stack pointer. Single-cycle register operations. 16-bit register file reduces fetches to memory. address bus allows direct access

Large

16-bit

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The CPU features

16-bit

data bus allows direct manipulation of word-wide arguments. Constant generator provides six most used immediate values and reduces code size. Direct memory-to-memory transfers without intermediate register holding. and byte addressing and instruction formats.

Word

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The Family

Broad family of TIs 16-bit microcontrollers from 1Kbytes ROM, 128 bytes RAM to 60Kbytes ROM, 10Kbytes RAM

Three subfamilies basic unit more features in LCD driver

MSP430x1xx: MSP430x3xx:

MSP430x4xx:built

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Part numbering convention

MSP430MtFaFbMc Mt : Memory type

C ROM, F Flash, P OTP, E EPROM Fa,Fb 10, 11 basic 12, 13 HW UART 14 HW UART, HW multiplier 31, 32 LCD Controller

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Part numbering convention

MSP430MtFaFbMc Mc : Memory capacity 0: 1 Kb ROM, 128 b RAM 1: 2 KB ROM, 128 b RAM 2: 4 KB ROM, 256 b RAM .... 9: 60 KB ROM, 2 Kb RAM

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MSP 430 Roadmap

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MSP 430 Modular Architecture

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MSP430 16-bit RISC

Large

16-bit register file eliminates single accumulator bottleneck 16bit data

High-bandwidth

and address bus with no paging

RISC architecture with 27

CPU Registers

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Registers: PC (R0)

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Each instruction uses an even number of bytes (2, 4, or 6) PC is word aligned (the LSB is 0)

MOV #LABEL,PC ; Branch to address LABEL MOV LABEL,PC ; Branch to address contained in LABEL MOV @R14,PC ; Branch indirect, indirect R14

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Registers: SP (R1)
Stack and

pointer for return addresses of subroutines interrupts SP is word aligned (the LSB is 0)

Pre-decrement/post-increment scheme 2(SP),R6 ; Item I2 > R6 R7,0(SP) ; Overwrite TOS with

MOV MOV

R7

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Registers: SR (R2)

C: SR(0) Z: SR(1) N: SR(2) GIE (Global interrupt enable): SR(3) CPUOff: SR(4) OSCOff: SR(5) SCG1, SCG0: SR(7), SR(6) V: SR(8)

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Constant Generators

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As source register addressing mode in the instruction word

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CISC / RISC Instruction Set

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27 Core RISC Instructions

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Emulated Instructions

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51 Total Instructions

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Double operand instructions

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Single Operand Instruction

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Jump Instructions

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3 Instruction Formats

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Addressing Modes

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Register Addressing Mode

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Register-Indexed Addressing Mode

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Symbolic Addressing Mode

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Absolute Addressing Mode

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Register Indirect Addressing Mode

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Register Indirect Auto increment Addressing Mode

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Immediate Addressing Mode

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Code Reduction Effect of Constant Generator

Machine Cycles for Format I Instructions

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Machine Cycles for Format II/III Instructions

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MSP430 Memory Model

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Memory Organization

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MSP 430 Architecture

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MSPx430x14x Architecture

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Watchdog Timer
WDT

module performs a

controlled system restart after a software problem occurs

Can serve as an interval timer (generates interrupts) WDT Control register is password protected

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Timer_A
Timer_A

is a 16-bit

timer/counter with three capture/compare registers

Capture

external

signals

Compare PWM mode SCCI latch for

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ADC12
High-performance

12-bit analog-to-digital converter

More

than 200 Ksamples/sec Programmable sample&

hold

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USART Serial Port

The

universal synchronous/ peripheral interface

asynchronous receive/transmit
(USART)

supports two serial modes with one hardware module

UART or SPI (Synchronous

Peripheral Interface) modes

Double-buffered

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interrupts

Topics to Cover

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qInterrupts qInterrupt Service Routines (ISRs) qProcessor Clocks

Interrupts

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Execution of a program proceeds predictably, with interrupts being the exception Interrupts are usually generated by hardware Processor stops with it is doing, Stores enough information to later resume,

Interrupts
Interrupt code runs in the foreground

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Interrupts preempt normal code execution

Normal (e.g. main()) code runs in the background

Interrupts can be enabled and disabled

Globally Individually on a per-peripheral basis Non-Mask able Interrupt (NMI)

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The occurrence of each interrupt is unpredictable

When an interrupt occurs Where an interrupt occurs

Interrupts are associated with a variety of on-chip and off-chip peripherals.

Timers, Watchdog, D/A, Accelerometer

Interrupts commonly used for

code

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Urgent tasks with higher priority than main

Infrequent tasks to save polling overhead Waking the CPU from sleep Call to an operating system (software

interrupt).

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Interrupt Service Routines

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Look superficially like a subroutine. However, unlike subroutines

ISRs can execute at unpredictable times. -Must carry out action and thoroughly clean up.

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Well-written ISRs:
Should be short and fast Should affect the rest of the system as little as possible Require a balance between doing very little thereby leaving the background code

with lots of processing and doing a lot and leaving the background code with nothing to do

Applications that use interrupts should:

Disable interrupts as little as possible Respond to interrupts as quickly as possible

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Interrupt-related runtime problems can be exceptionally hard to debug Common interrupt-related errors include:

Returning from ISR

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MSP430 requires 6 clock cycles before the ISR begins executing

The time between the interrupt request and the start of the ISR is called latency

An ISR always finishes with the

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Processor Clock Speeds

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Often, the most important factor for reducing power consumption is slowing the clock down
Faster clock = Higher performance,

 Another method to reduce power

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consumption is to turn off some (or all) of the system clocks

Active Mode (AM): CPU, all clocks, and enabled modules are active ( 300 ) LPM0: CPU and MCLK are disabled, SMCLK and

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timers
System timing is fundamental for real-time applications The MSP430F2274 has 3 timers, namely Watchdog, Timer_A, and Timer_B Timer_A and Timer_B may be triggered by internal or external clocks Timer_A and Timer_B also include multiple

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Timer Applications

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Pulse Width Modulation (PWM)

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Pulse width modulation (PWM) is used to control analog circuits with a processor's digital outputs PWM is a technique of digitally encoding analog signal levels The duty cycle of a square wave is modulated to encode a specific analog signal level

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Watchdog Timer

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The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a software problem occurs. After a power-up cycle (PUC), the WDT+ module is automatically configured in watchdog mode with an initial 32768 clock cycle reset interval using the DCOCLK.

 Watchdog or Interval modes

3/27/12 Features of the watchdog timer+ module include:

Access to WDT+ control register is password protected Control of RST/NMI pin function Selectable clock source (SMCLK or ACLK) Four software-selectable time intervals SMCLK: 32, 8, 0.5, 0.064 ms (1 MHz) ACLK: 1000, 250, 16, 1.9 ms (32Khz) Can be stopped to conserve power