CSC: 345 Computer Architecture

Jane Huang Lecture 3 Interrupts System Interconnections

Todays Overview
Any Questions? The instruction cycle Interrupts Interconnection Structures Group projects

Interrupts
A computer system must provide a method for allowing mechanisms to interrupt the normal processing. Interrupts improve processor efficiency Most external devices are much slower than the processor and busy waiting takes up too many resources. Examples:
External interrupts: Timing device, Circuit monitoring the power supply, I/O device requesting data or completed data transfer etc. Timeout errors. Internal interrupts (caused by an exception condition). Illegal use of an instruction or data (traps) example: register overflow, attempt to divide by zero, invalid op code, stack overflow etcTimer: OS system can perform operations on a regular basis. Software Interrupts Special call instruction that behaves like an interrupt.

Benefits of Interrupts
No Interrupts
1
WRITE

Interrupts -Short I/O wait.

4
I/O Command

1
WRITE 2a

4
I/O Command

2
END WRITE

Interrupt Handler 2b

5
WRITE END 3a

3
3b WRITE WRITE

Short I/O the I/O operation is completed within the time it takes to execute instructions in the program that occur before the next I/O command. The processor is kept busy the whole time. Long I/O - The next I/O command comes before first I/O has completed. Processor still needs to wait. Some time is saved !

No Interrupts
1 4 5
2

Interrupts -Short I/O wait.

1 4
2a

2b

3a

3b

Interrupts -Long I/O wait. (More realistic!)

1 4
2

An example
Busy Wait: Consider a computer that can execute two instructions that read the status register and check the flag in 1 s. Input device transfers data at an average rate of 100 bytes per second equivalent to one byte every 10,000 s. The CPU will check the flag 10,000 times between each transfer. Interrupt Driven: CPU could use this time to perform other useful processing.

Interrupt Cycle
The interrupt cycle is added to the instruction cycle. Processor checks for interrupt indicated by an interrupt flag. If there is NO interrupt Fetch next instruction If there is an interrupt:
Suspend operation of the program Save its context Set PC to start address of the interrupt handler Process the interrupt Restore the context of the original program and continue its execution.

Instruction Cycle with Interrupts

Following each execute cycle:

Check for interrupts Handle active interrupts

Instruction Cycle with Interrupts

Disable interrupts
Processor will ignore further interrupts whilst processing one interrupt Interrupts remain pending and are checked after first interrupt has been processed Interrupts handled in sequence as they occur

Define priorities
Low priority interrupts can be interrupted by higher priority interrupts When higher priority interrupt has been processed, processor returns to previous interrupt

Handling Multiple Interrupts

Sequential approach once an interrupt handler has been started it runs to completion
(+) Simpler (-) Does not handle priority interrupts well Example: Incoming data might be lost.

Nested approach a higher priority device can interrupt a lower priority one.
(+) More complex (-) Interrupts get handled in order of priority.

Priority Interrupts
Polling
One common branch address for all interrupts. Interrupt sources polled in priority sequence. If an interrupt signal is on, control branches to a service routine for this source. (-) Time overhead to handle many interrupts can be excessive. The operation can be sped up with a hardware priority-interrupt unit.

Daisy-Chain Priority
Hardware solution Serial connection of all devices that request interrupts. Device with the highest priority takes first position, 2nd highest takes 2nd position etc. Interrupt request line shared by all devices.

Daisy-chain Priority Interrupt

A Serial Approach
Processor data bus VAD 2 VAD 3 Device 2 PI P0 Device 3 PI P0

VAD 1 Device 1 PI P0

Interrupt Request

INT

CPU
INTACK

Interrupt Acknowledge

One stage of the daisy-chain Priority Arrangement

Priority In

PI

.
RF

.
PI Delay 0 0 1
Interrupt request to CPU

Vector Address

Interrupt request from device

S R

PO
Priority Out

RF 0 1 0 1

PO Enable 0 0 1 0 0 0 0 1

Open-collector inverter

From: Computer System Architecture, Morris Mano

Parallel Priority Interrupt

Uses a register whose bits are set separately by the interrupt signal from each device. Priority established according to the position of bits in the interrupt register. A mask register is used to control the status of each interrupt request. Mask bits set programmatically. Priority encoder generates low order bits of the VAD, which is transferred to the CPU. Encoder sets an interrupt status flip-flop IST whenever a nonmasked interrupt occurs. Interrupt enable flip-flop provides overall control over the interrupt system.

Parallel Priority Interrupt Hardware

Interrupt Register Disk Printer Priority Encoder

0 1

I0 I1 I2 I3 y x 0 0 0 0 0 0
Enable

Reader
From: Computer System Architecture, Morris Mano

2 3

Keyboard

0 1 2

IEN

IST

Interrupt to CPU

3
INTACK from CPU Mask Register

Priority Encoder
Circuit that implements the priority function. Logic if two or more inputs arrive at the same time, the input having the highest priority will take precedence. I0 1 Inputs I1 I2 d d I3 d Outputs d Y IST 0 0 1

0 0 0 0

1 0 0 0

d 1 0 0

d d 1 0

0 1 1 d

1 0 1 d

1 1 1 0

Boolean functions X = I0I1 Y = I0I1 + I0I2

IST = I0 + I1 + I2 + I3

Interrupt Cycle
The Interrupt enable flip-flop (IEN) can be set or cleared by program instructions. A programmer can therefore allow interrupts (clear IEN) or disallow interrupts (set IEN) At the end of each instruction cycle the CPU checks IEN and IST. If either is equal to zero, control continues with the next instruction. If both = 1, the interrupt is handled. Interrupt micro-operations:
SPSP 1 (Decrement stack pointer) M[SP] PCc Push PC onto stack INTACK 1 Enable interrupt acknowledge PC VAD Transfer vector address to PC IEN 0 Disable further interrupts Go to fetch next instruction

Software Routines for handling Interrupts

Software routines used to service interrupt requests and control interrupt hardware registers. Each device has its own service program reached through a jump instruction stored at the assigned vector address. Example: Keyboard sets interrupt bit whilst CPU is executing instruction at location 749. At the end of the instruction, 750 is pushed onto the stack, the VAD for the keyboard is taken off the bus and placed into the PC. Control is passed to the keyboard routine. Once completed, PC is replaced with original address of next instruction (750)
JMP DISK JMP PRINTER JMP READER JMP KEYBOARD Program to service magnetic disk. Program to service line printer.

Program to service character reader.

Main program Program to service Keyboard.

Stack

Small Group Activity

Consider a computer system that contains an I/O module controlling a simple keyboard/printer teletype. The following registers are contained in the processor and connected directly to the system bus:
INPR: OUTR: FGI: FGO: IEN: Input Register, 8 bits Output Register, 8 bits Input Flag, 1 Bit Output Flag, 1 Bit Interrupt Enable, 1 Bit

Keystroke input from the teletype and printer output to the teletype are controlled by the I/O module. The teletype is able to encode an alphanumeric symbol to an 8-bit word and decode an 8-bit word into an alphanumeric symbol. a. Describe how the processor using the first four registers listed in this problem, can achieve I/O with the teletype. b. Describe how the function can be performed more efficiently by also employing IEN. IF TIME: draw the circuit diagram for the priority encoder in the parallel priority interrupt hardware diagram.

Interconnection Structures
Memory: Outputs data. Inputs read, write, and timing signals, addresses, and data.

I/O Module. Outputs data & interrupt signals. Inputs control signals, data, and addresses.

CPU: Outputs address, control signals, and data. Inputs instructions data, and interrupt signals.

Bus Interconnection
Communication pathway connecting two or more devices. Shared transmission medium - usually broadcast. Typically 50 100s of separate lines divided into three functional groups:
Data lines At this level data and instruction are synonymous. Width is a key determinant of performance. (Example: 32 bit words, data bus 16 bits 2 cycles to transmit one word). Address lines Identify source or destination of data (ie address in memory) Width determines maximum memory capacity of system (ie 8080 has 16 bit address 64K address space). Control lines Control lines Control and timing signals (read, write, ack, clock)

Bus Interconnection

Parallel lines on circuit boards Ribbon cables Strip connectors on mother boards Sets of wires

Single Bus Problems

Lots of devices on one bus leads to:
Propagation delays Long data paths mean that co-ordination of bus use can adversely affect performance If aggregate data transfer approaches bus capacity

Most modern systems have at least 4 busses to solve this problem:

Processor bus Cache bus Dedicated bus for accessing system cache. Local I/O bus High speed I/O bus for connecting performance critical peripherals such as high-speed networks, disk storage devices. Standard I/O bus Connects slower peripherals such as mouse & modems etc.

Traditional ISA (with Cache)

High Performance Architecture

Elements of Bus Design

Type
Dedicated vs. Multiplexed Dedicated by functionality ie address vs. data or dedication to a physical subset of components.

Arbitration Method
Only one module can have control of the bus at any one time. Centralized vs. Distributed

Timing
Synchronous vs. Asynchronous

Bus Width
Address Data

Data Transfer Type

Read, Write, Read-modify-write, Read-after-write, Block

Bus Arbitration
Hardware arbitration
Serial arbitration daisy chain Parallel arbitration
Bus arbiter 1 Bus arbiter 2 Bus arbiter 3 Bus arbiter 4

Dynamic arbitration algorithms

System can change the priority of the devices during normal operation. Time slice fixed length time slice of bus time offered sequentially to each processor in round robin fashion. Polling address of each device in turn placed on polling lines. A device may activate bus busy if it is being polled. LRU Least recently used. FIFO First in first out. Rotating Daisy-chain dynamic extension of the daisy chain.
Bus Ready
Priority Encoder

2 X 4 Decoder

Hardware for parallel arbitration

Synchronous Timing
Occurrence of events on the bus coordinated by a clock. Bus includes a clock line. Clock transmits alternating 1s and 0s of equal duration. A single 1-0 transmission = 1 clock cycle. All events start at the beginning of a clock cycle.

Timing of Synchronous Bus Operations

Place stable address on the line during first clock signal. Once the address stabilizes an address enable signal is issued. Read: Read enable signal activated at start of next cycle. Memory module recognizes address and after 1 cycle places data on bus. Write is similar but address + data is placed on the bus early.

Stable Address

Valid Data In

Valid Data Out

Timing of Asynchronous Bus Operations

Occurrence of one event follows the occurrence of a previous event. For read place status and address on the line. Once stabilized, place a read signal on the bus. Memory decodes address, and places data on the bus. Processor sends and ACK all lines can then be dropped.

Data Transfer Type

Bus supports various data transfer types
Write (Master to slave) Read (Slave to master)

Multiplexed address/data bus

Write (Cycle 1 : Address, Cycle 2 : Data) Read (Cycle 1 : Address, Delay, Cycle ?: Data)

Non-multiplexed address/data bus

Write (Address & Data both sent in same cycle). Read (Address followed by data once address is stabilized)

Other types of transfer include:

Read after write Block data transfer (Address + multiple blocks of data)

Memory System Overview

Memory systems can be classified according to the following key characteristics:
Location External Peripherals such as disk and tape etc. Internal Main memory, Registers, Cache Capacity Unit of Transfer Access Method Performance Physical Type (What it is made of) Physical Characteristics (How it behaves) Organization

Memory Characteristics (cont)

Capacity
Expressed in bytes or words. Typical word lengths are 8, 16, 32 bits

Unit of Transfer
For internal memory this is equal to the number of data lines into and out of the memory module. Word length or longer (ie 64, 128, or 256 bits)

Concepts of Size
Word: Natural unit of organization within memory. No. or bits to represent a number, Length of one instruction. Many exceptions. Addressable Units: Either word or byte. Maximum addressable units = 2A (where A = no. of bits in the address) Unit of transfer No. of bits read into and out of memory. Addressable unit or larger (block)

Access Method
Sequential Access
Data organized into units called records. Access is linear sequenced. Shared read/write mechanism that is physically moved to read/write data. Access time varied. Example: Tape Unit.

Direct Access
Shared read/write mechanism Individual records have a unique physical address / location. Access by direct access to general vicinity + local sequential searching. Example: Disk Units.

Access Method
Random Access
Each addressable location in memory has a unique, physically wired addressing mechanism. Access time is independent of previous accesses. Access time is constant. Example: Main Memory + some Caches.

Associative:
Random access type of memory Supports comparison of desired bit locations within a word for a specified match on many words simultaneously Word is retrieved based on a portion of its contents rather than its address. Constant retrieval time Example: Many caches.

Performance
Access Time (latency)
Random Access = time taken to perform a read or write. Non-random access memory = time to position read-write mechanism at desired location.

Memory Cycle Time

Access time + additional time required before a second access can commence. Affected by behavior of the system bus not the processor.

Transfer Rate
Rate at which data can be transferred into or out of a memory unit. For random access memory = 1/(cycle time). Non random-access memory TN = TA + ( N / R)
TN = Average time to read or write N bits TA = Average access time N = Number of bits R = Transfer rate, in bits per second (bps)

Magnetic Disks
Tracks: Hard Disk platters arrange data into concentric circles, rather than one large spiral, as some other mediums use. Each circle is called a Track. Sectors: The smallest addressable unit on a Track. Sectors are normally 512 bytes in size, and there can be hundreds of sectors per track, depending on location. (Constant bit density more sectors on outer tracts) Heads: The devices used to write and read data on each platter. Cylinders: Platters on a hard disk are stacked up, and so are the heads. Concentric circles from each parallel platter form a cylinder. (Think Stargate!)

http://www.pcguide.com/ref /hdd/geom/tracksDifference -c.html

Reading and Writing

SEEK: Disk controller sends a command to move the arm over the proper track. = Seek Time. Seek time Minimum / Maximum Average? Sum of all possible seeks divided by the number of possible seeks. What is wrong with this??? Rotation latency (delay) Time for requested sector to rotate under the head. Average = halfway around disk. (0.5) If a disk rotates at 10,000 RPM Avg Rotation time = 0.5 / 10,000 RPM = 0.5 / (10,000/60) RPS = 0.0030 sec = 3.0 ms. Transfer time Time it takes to transfer a block of bits. (typically a sector) Function of block size, disk size, rotation speed, recording density, etc.

Example
What is the average time to read or write a 512-byte sector for a disk? The advertised average seek time is 5ms, the transfer rate is 40MB/sec, it rotates at 10,000 RPM, and the controller overhead is 0.1ms. Assume the disk is idle so that there is no queueing delay. In addition, calculate the time assuming the advertised seek time is three times longer than the measured seek time. Answer: Average disk access = average seek time + average rotational delay + transfer time + controller overhead.

5ms

0.5

+ 0.5KB

+ 0.1ms

10,000 RPM

40 MB/sec

= 1.67ms + 3.0ms + 0.013ms + 0.1ms = 4.783ms

Memory Hierarchy
Trade-offs Speed Cost Size

Next week: Memory and Cache