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M.KALYAN
7/3/12
Introduction
Need for higher speed and performance in applications is a driving requirement of any embedded system. Increasing processors clock not a solution and hence System on Chip (SoC) is emerging at such higher pace. But SoC faces a gap between productivity and time to market. Design complexity increases with multicore and other features
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SoC Design
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Interconnect topologies with multiple address, data, handshaking buses enable high performance and low latency They can no longer be verified with the standard directed testing methodologies. Greater amount of risk and pressures Verification of such new interconnections becomes much more complex.
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To address the gap between production and time to market. To make design verfication/testing simpler To avoid integration mismatches in SoC
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AMBA (ARM) CoreConnect (IBM) Sonics Smart Interconnect (Sonics) STBus (STMicroelectronics) Wishbone (Opencores) Avalon (Altera) PI Bus (OMI) MARBLE (Univ. of Manchester) (PalmChip)
CoreFrame 7/3/12
AMBA Protocol
AMBA is an open standard, onchip bus specification by ARM ltd. AMBA enhances a reusable design methodology by defining a common backbone for SoC modules. It is now widely used on a range ofASIC and SoC parts, applications processors used in modern portable mobile devices.
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The AMBA specification has been derived to satisfy four key requirements:
to be technology-independent and be appropriate for full-custom, standard cell and gate array technologies encourage modular system design to improve processor independence minimize the silicon infrastructure required to support efficient on-chip and off-chip communication
to to
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AMBA 3 Specifications
AMBA 3defines four buses/interfaces:
Advanced eXtensible Interface (AXI) Advanced High-performance Bus (AHB) Advanced System Bus (ASB) Advanced Peripheral Bus (APB)
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AHB, wait
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Arbitration
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AMBA ASB is an alternative system bus suitable for use where the highperformance features of AHB are not required. ASB also supports the efficient connection of processors, on-chip memories and off-chip external memory interfaces with low-power peripheral macrocell functions.
Burst transfers, pipelined transfer operation, multiple bus master are 7/3/12some of its features.
The AMBA APB is for low-power peripherals. AMBA APB is optimized for minimal power consumption and reduced interface complexity to support peripheral functions. APB can be used in conjunction with either version of the system bus.
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APB transfers
Write transfer
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Read transfer
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AXI Features
Out of order completion Multiple outstanding bursts Burst addressing Channel architecture Registers Slices
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BRIDGING
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AMBA 2 Vs AMBA 3
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Conclusion
Powerful verification IP, tools like RVM from Synopsys allow designers to reduce the overall design cycle in designing the products using AMBA technology.
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OU KY AN TH
Any Queries?
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References
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IHI0011A_AMBA_SPEC.pdf & IHI0022D2c_amba_axi_protocol_spec_bet a from http://arm.com Designing with AMBA AXI by Mic Posner, Synopsis & VCI interface and AMBA bus Design reuse pdfs from http://whereisdoc.com AMBA Bus from http://wikipedia.com
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