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8-1
Introduction
Digital IC technology has advanced rapidly(Chap 4)
Complexity Small- scale integration(SSI) Medium- scale integration(MSI) Large- scale integration(LSI) Very large- scale integration(VLSI) Ultra large- scale integration(ULSI) Giga- scale integration(GSI) Tera- scale integration(TSI) Number of Gates Fewer 12 to 99(10 - 10 ) 100 to 9,999(10 - 10 ) 10,000 to 99,999(10 - 10 ) 100,000 to 999,999(10 - 10 ) 1,000,000 or more(10 - 10 ) (10 or more)
12 9 11 7 9 5 7 3 5 2 3
Moores Law
The number of components that can be packed on a computer chip doubles every 18 months while price stays the same.
Most of the reasons that modern digital systems use integrated circuits q Integrated circuits pack a lot more circuitry in a small package
the overall size of any digital system is reduced
s
the cost is dramatically reduced because of the economies of mass-producing large volumes of similar devices
Integrated circuits have made digital systems more reliable by reducing the number of external interconnections
Discrete components(transistor, diode, resistor, etc.) are protected from poor soldering, breaks or shorts in connecting paths on a circuit board
Digital Systems
8-2
Integrated circuits have drastically reduced the amount of electrical power needed to perform a given function
Integrated circuitry typically requires less power than their discrete counterparts
s s
the saving in power supply costs a system does not require as much cooling
There are some things that Integrated circuits cannot do q Integrated circuits can not handle very large currents or voltages (because the heat generated in such small spaces would cause temperatures to rise beyond acceptable limits) q Integrated circuits can not easily implement certain electrical devices such as inductors, transformers, and large capacitors For these reason
q
Integrated circuits are principally used to perform low-power circuit operations that are commonly called information processing The operations that require high power levels or devices that can not be integrated are still handled by discrete components
* Transistor carrier 1) Electron Hole, Bipolar 2) Electron Hole Unipolar
Korea Univ. of Tech. & Edu. Dept. of Info. & Comm.
Various Logic Families q Bipolar transistors : TTL and ECL q Unipolar MOSFET transistors : NMOS, PMOS, and CMOS
Digital Systems
8-3
In this chapter q We will present the important characteristics of each of IC families q You will be much better prepared to do analysis, troubleshooting, and some design of digital circuits
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VIL (max) : low- level input voltage VOH (min) : high- level output voltage VOL (max) : low- level output voltage IIH : high- level input current IIL : low- level input current IOH : high- level output current IOL : low- level output current
Actual current direction : Fig. 8-5
Fan-Out( = Loading Factor ) q maximum number of standard logic inputs that an output can drive reliably
Fan-Out = 10 : one logic gate can drive 10 standard logic inputs
Digital Systems
8-4
Propagation Delays : Fig. 8-2 (INVERTER) q tPLH : delay going from LOW to HIGH
q
Power Requirements q Every IC requires a certain amount of electrical power to operate. q Power supply terminal on a chip : VCC(for TTL), VDD(for MOS)
q
Average Current
ICC(avg) = ( ICCH + ICCL ) / 2
Average Power
PD(avg) = ICC(avg) X VCC
Speed-Power Product q Digital IC families have historically been characterized for both speed and power
shorter gate propagation delays(higher speed) lower values of power dissipation
q
Digital Systems
8-5
= 50 Pico-joules (pJ)
Noise Immunity q Stray electric and magnetic fields can induce voltages on the connecting wires between logic circuits
These unwanted, spurious signals are called noise
q
Noise Immunity
Circuits ability to tolerate noise without causing spurious changes in the output voltage
High-state noise margin : VNH = VOH (min) - VIH (min) Low-state noise margin : VNL = VIL (max) - VOL (max)
Exam. 8-1) Determine the following by using Tab. 8-1 q (a) The maximum-amplitude noise spike that can be tolerated when a HIGH output is driving an input : VNH = VOH (min) - VIH (min) = 2.4 V - 2.0 V = 0.4 V
q
(b) The maximum-amplitude noise spike that can be tolerated when a LOW output is driving an input : VNL = VIL (max) - VOL (max) = 0.8 V - 0.4 V = 0.4 V
Chap. 8 Integrated-Circuit Logic Families
Korea Univ. of Tech. & Edu. Dept. of Info. & Comm.
Digital Systems
8-6
Invalid Voltage Levels q Invalid Voltage Level : Input voltage between 0.8 and 2.0 V
produce an unpredictable output response
q
In normal operation, a logic input voltage will not fall into the invalid region (because it comes from a standard logic output) Invalid Input Voltage Level
1) Output is overloaded (= its fan-out is exceeded) 2) Power-supply voltages are outside the acceptable range
Current Sourcing/ Current Sinking Action q Current Sourcing Action : Fig. 8-5(a)
When the output of gate 1 is in the HIGH state
s
the output of gate 1 is acting as a source of current for the gate 2 input
the output of gate 1 is acting as a sink of current for the gate 2 input
8-7
Saturate Region
IC IB
ON
Active Region
OFF
VCE
Cut-off Region
VCE(sat)
Transistor Characteristic
Diode equivalent of the multiple-emitter Tr. Q1 : Fig. 8-7(b) q Diodes D2 and D3 : two E-B junctions of Q1 VBE(on) = 0.7 V q Diode D4 : C-B junction of Q1 VCE(sat) = 0.1 V - Ge Circuit Operation - LOW output state : Fig. 8-8(a)
0.2 V - Si
q
Q3 ON VCE (Q4) + VD1 + VBE (Q3) = 0.1 V + 0.7 V + 0.7 V = 1.5 V 0.8 V Q3 OFF Chap. 8 Integrated-Circuit Logic Families
Korea Univ. of Tech. & Edu. Dept. of Info. & Comm.
Digital Systems
8-8
Circuit Operation - HIGH output state : Fig. 8-8(a) q VOH will be around 3.4 to 3.8 V
5 V (Vcc) - VBE (Q3) - VD1 = 5 V - 0.7 V - 0.7 V = 3.6 V
q
R1, R2, R3, and R4 in Fig. 8-8 q R1 : A B 0 , R1 Vcc Ground Short q R2 : R2 Q2 ON/OFF Q3 Base Vcc Q3 ON . q R3 : R3 Q2 Q4 Darlington hFE = hFE (Q2) X hFE (Q4) . q R4 : Q3 ON . Current-Sinking Action : Fig. 8-9(a)
q
Current-Sourcing Action : Fig. 8-9(b) q Q3 : Current-sourcing transistor or Pull-up transistor q IIH : small reverse-bias leakage current (typically 10 A)
Fig. 8-8(a)
Digital Systems
8-9
Q3 Q4 .
Q3 Q4 ON (5 V / 130 = 40 mA) .
This low output impedance provides a short time constant for charging up any capacitive load on the output impedance , impedance ( ).
So there is a period of a few nanoseconds during both transistors are conducting (ON) Relatively large current (30 to 40 mA) will be drawn from the power supply.
The same totem-pole arrangement as the NAND gate is used Output HIGH : Input A = B = 0
Q1 = Q2 = ON, Q3 = Q4 = OFF, Q5 = ON, Q6 = OFF
Digital Systems
8-10
No longer recommended by the manufacturers for use in new design Still enough demand in the market to keep them in production
Manufacturers Data Sheets q Data Sheet for 5400/7400 NAND gate : Fig. 8-11
Recommended operating conditions, Electrical characteristics, and Switching Characteristics are shown Paragraph Data Sheet
Digital Systems
8-11
Supply Voltage and Temperature Range q 74 and 54 have nominal supply voltage VCC = 5 V
q
Supply Voltage
74 operate reliably from 4.75 to 5.25 V 54 operate reliably from 4.5 to 5.5 V
Temperature Range
74 operates from 0 to 70 C 54 operates from -55 to +125 C
Digital Systems
8-12
Fan-Out : Sec. 8-5 q Typically drive 10 standard TTL inputs : Exam. 8-5
LOW Output : Current Sink
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* + : - :
Exam. 8-2) Determine the maximum average power dissipation and the maximum average propagation delay of a single gate q PD (max) = ICC (max) X Vcc(max) = 15 mA X 5.25 V = 78.75 mW
8-13
Si
=
0.2 0.4 0.6 V
from ON to OFF
Forward Bias
Schottky Transistor
Korea Univ. of Tech. & Edu. Dept. of Info. & Comm.
8-14
74LS : Low-power Schottky TTL q Lower-power (2 mW) q Slower-speed (9.5 ns) 74AS : Advanced Schottky TTL
q q
Fastest TTL series (1.7 ns) 74AS compare with 74S : Tab. 8-4
74ALS : Advanced Low-power Schottky TTL q Lowest speed-power product (4.8 pJ) q Lowest gate power dissipation (1.2 mW) q 74ALS compare with 74LS : Tab. 8-5 74F : Fast TTL
q q
74AS 74ALS
Comparison of TTL Series Characteristics : Tab. 8-6 Exam. 8-3) Calculate the dc noise margins for a 74LS IC, and compare with the standard TTL noise margins. q 74LS : VNH = VOH (min) - VIH (min) = 2.7 V - 2.0 V = 0.7 V (Standard = 0.4 V)
Digital Systems
VNL = VIL (max) - VOL (max) = 0.8 V - 0.5 V = 0.3 V (Standard = 0.4 Chap. 8 Integrated-Circuit Logic Families V)
8-15
Exam. 8-4) Which TTL series can drive the most device inputs of the same series? q Series Fan-out series Tab. 8-6 . input drive series 74AS series 40 . series series IOL, IIL, IOH , IIH Sec.8-5 .
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IOL : sum of IIL currents from each input But not zero : produce a voltage drop VOL VOL must not exceed VOL(max) : 0.4 Volt
IOH : sum of IIH currents from each input VOH must not be lower than VOH(min) : 2.4 Volt
Determining the Fan-Out q An IC output can drive how many different inputs
Digital Systems
8-16
Exam. 8-5) How many 7400 NAND gate inputs can be drive by a 7400 NAND gate output? q Refer to the data sheet in Fig. 8-11 (p. 431) Fan-out(LOW) : Fig. 8-14
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Fan-out(HIGH)
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Exam. 8-6) How many 74ALS20 NAND gate inputs can be drive by the output of another 74ALS20 NAND gate? q Refer to the data sheet in Appendix (p. 841)
Fan-out(LOW)
s
Fan-out(HIGH)
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Overall Fan-Out = 20
Lower of the two values ( 80 and 20 )
Digital Systems
8-17
Fan-Out in Combination of various logic families q Method for determining the loading of any digital output
Step 1 : Fan-Out (HIGH)
s s
Add up the IIH for all inputs connected to an output. This sum must be less than the outputs IOH specification Add up the IIL for all inputs connected to an output. This sum must be less than the outputs IOL specification
Exam. 8-7) Determine if there is a loading problem (when A 74ALS00 NAND gate outputs is driving three 74S gate inputs and one 7406 gate input). q Refer to the data sheet in Tab. 8-7 (p. 441)
Step 1 : Fan-Out (HIGH)
s s
Add all IIH = Total IIH = 3 ( IIH for 74S ) + 1 (IIH for 74 ) = 3 ( 50 A ) + 1( 40A ) = 190 A This sum 190 A < 400 A ( IOH ) : No Problem Add all IIL = Total IIL = 3 ( IIL for 74S ) + 1 (IIL for 74 ) = 3 ( 2 mA ) + 1( 1.6 mA ) = 7.6 mA This sum 7.6 mA < 8 mA ( IOL ) : No Problem Chap. 8 Integrated-Circuit Logic Families
Korea Univ. of Tech. & Edu. Dept. of Info. & Comm.
Digital Systems
8-18
Exam. 8-8) The output could drive how many additional 74ALS inputs without being overloaded in Exam. 8-7 ? q Refer to the data sheet in Tab. 8-7 (p. 441)
Additional current in LOW = IOL - IIL(sum of load) = 8 mA - 7.6 mA = 0.4 mA
s
IIL = 0.1 mA, drive up to four more 74ALS inputs IIH = 20 A, drive up to ten more 74ALS inputs
Additional current in HIGH = IOH - IIH (sum of load) = 400 A - 190 A = 210 A
s
Exam. 8-9) What is the maximum number of F/F CLR inputs that this gate can drive? The output of a 74AS04 inverter is providing the CLR signal to a parallel register(74AS74 D F/F) q Refer to the 74AS74 data sheet (not in Appendix)
* PRE and CLR input of 74AS74 : IIL = 1.8 mA, IIH = 40 A * Output of 74AS04 : IOL = 20 mA, IOH = 2 mA
Maximum number of inputs(LOW)
s
IOH / IIH = 2 mA / 40 A = 50 IOL / IIL = 20 mA / 1.8 mA = 11.11 Chap. 8 Integrated-Circuit Logic Families
Korea Univ. of Tech. & Edu. Dept. of Info. & Comm.
q
Digital Systems
Overall Fan-Out = 11
8-19
Unused Inputs q 3
s
2) Connected to +5 V through a 1 k resistor : Fig. 8-15(b) s NAND, AND gate 1 k resistor is for current protection of the emitter-base NOR, OR junctions in case of spikes on the power supply line. 1 GND 3) Tied to a used input : Fig. 8-15(c)
s s
This technique can be used for any type of gate Tied input do not exceed fan-out current : Exam. 8-10
Digital Systems
Tied-Together Inputs q When two (or more) TTL inputs on the same gate are connected together Korea Univ. of Tech. & Edu.
Chap. 8 Integrated-Circuit Logic Families
Dept. of Info. & Comm.
8-20
Act as single input regardless of number tied together The reason for this characteristics : Fig. 8-8(b), p. 427
If input A and B are tied together and grounded, IIL is not changed (IIL is only limited by the R1)
s
This situation is different for OR and NOR gates : Fig. 8-10, p. 429
OR and NOR gates do not use multiple-emitter transistor (OR and NOR gates have separate input transistor for each input)
Exam. 8-10) Determine the load current at the output X in Fig. 8-16. ( Each gate is a 74LS, IIL = 0.4 mA, IIH = 20 A )
q q
Biasing TTL Inputs Low q One-shot trigger on a positive transition : Fig. 8-17
Resistor R serves to keep the T input LOW while switch is open
q
Digital Systems
8-21
Exam. 8-11) Determine an acceptable value for R ( OS gate is a 74LS TTL, IIL = 0.4 mA )
q q
Rmax = VIL(max) / IIL = 0.8 V / 0.4 mA = 2000 Standard resistor value for a good choice = 1.8 k
Current Transients : Fig. 8-18 q Whenever a totem-pole TTL output goes from LOW to HIGH, a high amplitude current spike is drawn from the Vcc supply.
V=L(di/dt) dt = 2 ns V .
:
s
Q4 saturated (ON) Q3 switching time Q3 Q4 ON (about 2 ns) Power Supply Line (PCB Pattern Line) distributed inductance surge current (30 to 50 mA) Voltage spike
Connect a 0.01 F or 0.1 F ceramic capacitor between Vcc and Ground near each TTL IC to short out high frequency spikes
Bypass Capacitor
s
The Capacitor leads are kept very short to minimize series inductance
Connect single large capacitor ( 2 to 20 F ) between Vcc and Ground on each board to filter out relatively low frequency variations in Vcc
Digital Systems
8-22
Suppose that the Gate A output = HIGH and the Gate B output = LOW
One gate output is trying to go LOW while another gate output is trying to go HIGH (when they are tied together) * Standard TTL IOH = IOL : as high as 50 mA I = 0.4 mA, I = 16 mA
s
OH
OL
MOS and CMOS behave less predictably when outputs are tied together
HIGH (= Q4 OFF) : voltage drop will not lower the output voltage below VOH(min) = 2.4 V LOW (= Q4 ON ) : current through Q4 will be limited to a value below IOL(max) = 16mA Chap. 8 Integrated-Circuit Logic Families
Korea Univ. of Tech. & Edu. Dept. of Info. & Comm.
8-23
Wired-AND Connection q Wired-AND operation using open collector gates : Fig. 8-21
Devices with OC Outputs can be connected together safely Dotted AND gate symbol eliminates the need for an actual AND gate : much slower switching speed than totem-pole outputs
s s
Totem-pole outputs have a pull-up TR (Q3) to change up load capacitance rapidly OC circuits should not be used where speed is a principal consideration
Output TR sinks the 25 mA of lamp current, LAMP = ON Output TR turns off, no path for current, LAMP = OFF
Korea Univ. of Tech. & Edu. Dept. of Info. & Comm.
Q=0
s
Digital Systems
8-24
Q=0
s
Tristate : A third type of TTL output configuration q Three possible output states : HIGH, LOW, High-Impedance
High-impedance (= Hi-Z)
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both transistor are turned off in the totem-pole arrangement output terminal is an open or floating (neither a LOW not A HIGH)
q q
Utilize the high-speed operation of the totem-pole arrangement Permit outputs to be connected together
Tristate TTL INVERTER : Fig. 8-25 q Obtained by modifying the basic totem-pole circuit : refer to Fig. 8-7, p. 426
1) Enabled State ( E = 1) : Q1 = OFF A Q1 , D2 = OFF
s s
when A = 0 : Q1= ON, Q2 = OFF, Q3 = ON, Q4 = OFF, X = 1 when A = 1 : Q1= OFF, Q2 = ON, Q3 = OFF, Q4 = ON, X = 0
2) Disabled State ( E = 0 ) : Q1 = D2 = ON
s s
Q2 = OFF D2 = ON Q3 = OFF, Q2 = OFF Q4 OFF Output = Hi-Z ( Q3 = Q4 = both OFF ) Chap. 8 Integrated-Circuit Logic Families
Korea Univ. of Tech. & Edu. Dept. of Info. & Comm.
Digital Systems
8-25
Advantage of Tristate q Outputs can be connected together (paralleled) without sacrificing switching speed.
When Enabled, Totem-pole outputs have a high-speed characteristic
q
Control the passage of a logic signal from input to output Two commonly used tristate buffer ICs : 74LS125, 74LS126
s s
Differ only in the active state of ENABLE input ( E) Contain four noninverting tristate buffers (14 pin)
Tristate buffers used to connect several signals to a common bus : Fig. 8-27
Transmit any one of A, B, and C signals over the bus line to other circuits by enabling the appropriate buffer No more than one output should be enabled at one time : Only signal B is enabled
s
Other Tristate ICs : 74LS374 (Octal D-type FF with tristate output) q 8-bit register made up of D-type FFs q Outputs are connected to tristate buffers
Digital Systems
8-26
ECL increases overall switching speed by preventing transistor saturation ECL is referred to as current-mode logic (CML)
Vc1 = 0 V Vc2 = - 0.9 V : R2 = 300 x 3 mA (IE) = -0.9 V Vc1 = - 0.9 V : R1 = 300 x 3 mA (IE) = -0.9 V Vc2 = 0 V Chap. 8 Integrated-Circuit Logic Families
Korea Univ. of Tech. & Edu. Dept. of Info. & Comm.
Digital Systems
8-27
q q
Vc1 and Vc2 are the complements of each other Output voltage levels are not the same as input voltage level : Fig. 8-29(b) addition of emitter follower
s
VC1 - VBE
Vc1 - 0.8 V : 0 V - 0.8 V = - 0.8 V (logic 1), - 0.9 V - 0.8 V = 0.7 V (logic 0)
s s
Emitter follower provides a very low output impedance ( 7 ) for large fan-out and fast charging of load capacitance Emitter follower produces two complementary output :
Logic levels
-0.8 V for logical 1 -1.7 V for logical 0
q
Digital Systems
8-28
q q
No noise spikes
Current switching
ECL compares with the TTL logic families : Tab. 8-8 q High speed (short propagation delay) : high clock rate q High power dissipation q Low noise margin Disadvantage of ECL
q
q q q
Relatively low noise margins and high power dissipation 2 Negative power supply voltage ( VEE and VBB ) Difficult to use ECL devices with TTL or CMOS ICs
Logic levels are not compatible with other logic families
Chap. 8 Integrated-Circuit Logic Families
Korea Univ. of Tech. & Edu. Dept. of Info. & Comm.
Digital Systems
8-29
Digital Systems
8-30
Schematic symbols for enhancement MOSFETs : Fig. 8-31 q N-channel/P-channel : Gate, Drain, Source Basic MOSFET Switch q N-channel MOSFET switching state : Fig. 8-32
OFF state : VGS = 0 Volt (ROFF = 1010 = open circuit) ON state : VGS = + 5 Volt (RON = 1 k)
q q
Threshold voltage (VT) = 1.5 V N- and P-channel switching characteristics : Tab. 8-9
P-channel MOSFET uses voltages of the opposite polarity
s
P- MOS
Uses only P- channel enhancement MOSFETs High density No longer part of new designs
Digital Systems
8-31
Q2 : acts as switch
N-MOS NAND gate : Fig. 8-34(a) Fig. 5-3 (p. 184) N-MOS NOR gate : Fig. 8-34(b) Fig. 5-10 (p. 189) N-MOS Flip-Flops q Two N-MOS NOR gates or NAND gates can be cross-coupled
s
Digital Systems
8-32
Operating Speed q 50 ns propagation delay for typical N- MOS NAND gate Noise Margin q Typically 1. 5 V for N- MOS with VDD = 5 V
Proportionally higher for larger VDD Fig. 8-39
Time-constant
Large ROUT ( > 1010 ) and CLOAD (2 - 5 pF) serve to increase switch time
Fan-out q Around 50 Power Drain q Low power dissipation because of large resistances
VIN = 0 V
s s s
RON (Q1) = 100 k, ROFF (Q2) = 1010 ID = 0. 5 nA : current from VDD supply PD = 5 V x 0. 5 nA = 2. 5 nW RON (Q1) = 100 k, RON (Q2) = 1 k ID = 5 V / 101 k = 50 A PD = 5 V x 50 A = 0.25 mW
VIN = + 5 V
s s s
8-33
Static Sensitivity q Static charge damage breaks down thin oxide films dielectric insulation q Precautions to protect from ESD (ElectroStatic Discharge)
1) Connect the chassis of all test instruments, soldering-iron tips, and your work bench to earth ground 2) Connect yourself to earth ground with a special wrist strap 3) Keep ICs in conductive foam or aluminum foil 4) Avoid touching IC pins, and insert the IC into the circuit immediately after removing it from the protective carrier 5) Place shorting straps across the edge connectors of PC boards when the boards are being carried or transported 6) Do not leave any unused IC inputs unconnected, because open inputs tend to pick up stray static charges
Digital Systems
8-34
Functionally equivalent
logic function must be same (6 D F/F with positive edge clock)
Electrically compatible
two ICs can be connected directly to each other (without taking any special measures to ensure proper operation)
Digital Systems
8-35
4000/ 14000 series q Oldest series (RCA) q Very low power dissipation q 3 to 15 V power- supply voltages q Very slow q Very low output current capability q Not pin- compatible with any TTL series q Not electrically- compatible with any TTL series 74C series
q q q
Pin- compatible and functionally equivalent to TTL with same number Performance much like 4000 series
74HC/ HCT (high- speed CMOS) q 10 times faster than 74C series q Pin- compatible and functionally equivalent q 74HCT devices electrically compatible with TTL q 74HC devices not electrically compatible
Digital Systems
8-36
74AC/ ACT (advanced CMOS) q Functionally equivalent to TTL q Not pin- compatible with TTL q 74AC not electrically compatible q 74ACT is electrically compatible q Faster than HC series q Device numbering different
74AC11004 = 74HC04 74ACT11293 = 74HCT293
74AHC (advanced high- speed CMOS) q Newest series q Three times faster than HC series q Direct replacement for HC series BiCMOS logic (Bipolar + CMOS)
q q q
Low- power of CMOS (75 % reduction over 74F family) + High- speed of Bipolar Pin-compatible with TTL and standard 5 V logic 74ABT : Advanced BiCMOS (second generation of BiCMOS)
high speed and 3.3 V low voltage
Chap. 8 Integrated-Circuit Logic Families
Korea Univ. of Tech. & Edu. Dept. of Info. & Comm.
Digital Systems
8-37
Noise Margins q CMOS devices have greater noise margins than TTL
High-state noise margin : VNH = VOH (min) - VIH (min) Low-state noise margin : VNL = VIL (max) - VOL (max)
8-38
74HC/ HCT series NAND : tpd = 8 ns 74AC/ ACT series NAND : tpd = 4.7 ns 74AHC series NAND : tpd = 4.3 ns
:
Unavoidable existence of parasitic (unwanted) PNP and NPN transistors embedded in the substrate of MOS ICs Devices maximum voltage ratings are exceeded (surge from power supply)
Digital Systems
8-39
:
Modern CMOS ICs are designed with protection circuitry (to prevent Latch-up) Well regulated power supply Clamping diode can be connected externally to protect against such transients Unused inputs must be connected to GND or VDD
Example of Texas Instrument : Tab. 8-12 Logic Family Life Cycle : Fig. 8-40
s
Digital Systems
8-40
Open-Drain Outputs : Fig. 8-43(a) q N-channel MOSFET only (no P-channel MOSFET)
Can connect together to get wired-AND : same as TTL open collector External pull-up resistor is needed Refer to Fig. 8-27 (p. 455) Tristate Outputs : Fig. 8-43(b)
q q
CMOS tristate outputs can be connected together : same as TTL tristate Only one output is enabled at one time
Input can be either digital or analog signals 4016/74HC4016 Quad bilateral switch : Fig. 8-45
Independently controlled : CONTA, CONTB, CONTC, CONTD Bi-directional : IN/OUTA, OUT/INA
Exam. 8-11) Describe the operation of the circuit of Fig. 8-46 q OUTPUT SELECT = HIGH : upper s/w = open, lower s/w = closed (Y = V ) IN q OUTPUT SELECT = LOW : upper s/w = closed, lower s/w = open (X = V ) IN q 4316/74HC4316 : second power supply ( -VEE), VOUT = from - VEE to + VDD
Digital Systems
8-41
8-19 IC Interfacing
Interface q Connecting the output(s) of one circuit or system to the input(s) of another circuit or system Input/Output currents with a supply voltage of 5 V : Tab. 8-15
q
CMOS input current requirement : No problem q TTL output current (74LS : IOH = 20 A) > CMOS input current (4000B : IIH = 1 A) CMOS input voltage requirement : Problem Refer to Tab. 8-10 (p. 473) q TTL output voltage (74LS : VOH = 2.4 V) < CMOS input voltage (4000B : VIH = 3.5 V)
q
Pull-up register : TTL output to rise to approximately 5 V, Fig. 8-47 1) Use open-collector IC : 7407 with pull-up, Fig. 8-48 2) Use voltage level-translator IC : 40104
Chap. 8 Integrated-Circuit Logic Families
Korea Univ. of Tech. & Edu. Dept. of Info. & Comm.
Digital Systems
8-42
CMOS Driving TTL in the HIGH State : Fig. 8-49(a) q CMOS output voltage(4000B : VOH = 4.95 V) > TTL input voltage (74LS : VIH = 2.0 V)
No problem in the HIGH state
q
Refer to Tab. 8-13 (p. 485) Refer to Tab. 8-10 (p. 473) min
CMOS output current(4000B : IOH = 0.4 mA) > TTL input current (74LS : IIH = 20 A) No problem in the HIGH state
CMOS Driving TTL in the LOW State : Fig. 8-49(b) q CMOS output voltage(4000B : VOL = 0.05 V) < TTL input voltage (74LS : VIL = 0.8 V)
No problem in the LOW state
q
max
CMOS output current(4000B : IOL = 0.4 mA) = TTL input current (74LS : IIL = 0.4 mA) No problem in driving a single TTL load
1 74LS 74LS125 Buffer IC : Fig. 8-51 4000B (IOL = 0.4 mA) can not drive even one input of 74 (IIL = 1.6 mA), 74AS (IIL = 2 mA), and 74ALS (IIL = 100 mA)
Digital Systems
8-43
Exam. 8-13) a) How many a 74HC output can drive 74LS inputs. b) How many a 4000B output can drive 74LS inputs. q a) IOL = 4 mA (74HC) , IIL = 0.4 mA (74LS) : fan-out = 10
q
Exam. 8-14) a) How many a 74HC output can drive 74ALS inputs. b) How many a 74HC output can drive 74AS inputs. q a) IOL = 4 mA (74HC) , IIL = 100 A (74ALS) : fan-out = 40
q
IOL = 4 mA (74HC) , IIL = 2 mA (74AS) : fan-out = 2 ( 3 ) IOL = 0.4 mA (4001B) , IIL = 0.4 mA (74LS) : fan-out = 1 ( 3 )
High-Voltage CMOS Driving TTL q Use voltage-level translator IC : 4050B, Fig. 8-52
s
Digital Systems
8-44
Exam. 8-17) Design a circuit to interface the temperature sensor to the digital circuit.
- The digital system alarm must sound when the temperature exceeds 100 F - The output voltage of LM34 temperature sensor goes up 10 mV per degree F q Voltage output of the LM34 at 100 F = 100 F X 100 mV/ F = 1 V Vref = - voltage input q Choose a bias current = 500 A, R = 5 V / 500 A = 10 K q Voltage divider 1 V : 4 V = 2 K : 8 K , Fig. 8-53
8-23 Troubleshooting
Logic Pulser : Fig. 8-54 q Logic pulser generates a short-duration pulse by pressing a pushbutton q Logic pulser senses the existing voltage level at the node and produces a voltage pulse in the opposite direction
if node = LOW : produce a narrow positive-going pulse if node = HIGH : produce a narrow negative-going pulse almost shorted circuit q Logic pulser has a very low output impedance (2 or less), so that it can overcome the NAND gates output and can change the voltage at the node.
Logic pulser can not produce a voltage pulse at a node that is shorted directly to ground or Vcc. Using Logic Pulser and Probe to Test a Circuit : Fig. 8-54 q Logic pulser manually injects a pulse into a circuit q Logic probe monitors the circuits response q Logic pulser is applied to the circuit node without disconnecting the output of NAND gate
q
Digital Systems
8-45
Finding Shorted Nodes q Press the logic pulser button (when you touch a logic pulser and a logic probe to the same node)
if the probe = constant LOW : the node is shorted to ground if the probe = constant HIGH : the node is shorted to Vcc
The Current Tracer q Current tracer detects a changing current in a wire or PCB trace without breaking the circuit q Current tracer senses a changing magnetic field produced by a changing current and causes a small indicator LED to flash
Insulated tip contains a magnetic pickup coil, and the tip is placed at a point in the circuit
q
Current tracer is used with a logic pulser to trace the exact location of shorts to ground or Vcc ) Node X is shorted to ground through the internal short at gate 2s input Tracer indicates no current pulse : Fig. 8-55(a) Tracer indicates presence of current pulse : Fig. 8-55(b) This prove that the short to ground is inside gate 2s input rather than gate 1s output
Digital Systems